On Wed, Jan 15, 2025 at 09:55:14AM +, Alexandru Elisei wrote:
> Hi Drew,
>
> On Tue, Jan 14, 2025 at 07:51:04PM +0100, Andrew Jones wrote:
> > On Tue, Jan 14, 2025 at 05:17:28PM +, Alexandru Elisei wrote:
> > ...
> > > > > +# $arch will have changed when cross-compiling.
> > > > > +[ -z "$
Hi Drew,
On Tue, Jan 14, 2025 at 07:51:04PM +0100, Andrew Jones wrote:
> On Tue, Jan 14, 2025 at 05:17:28PM +, Alexandru Elisei wrote:
> ...
> > > > +# $arch will have changed when cross-compiling.
> > > > +[ -z "$processor" ] && processor=$(get_default_processor $arch)
> > >
> > > The fact t
Hi Drew,
On Tue, Jan 14, 2025 at 07:39:49PM +0100, Andrew Jones wrote:
> On Tue, Jan 14, 2025 at 05:03:20PM +, Alexandru Elisei wrote:
> ...
> > diff --git a/configure b/configure
> > index 86cf1da36467..1362b68dd68b 100755
> > --- a/configure
> > +++ b/configure
> > @@ -15,8 +15,8 @@ objdump=
Hello,
> Few code simplifications without functional impact. Not tested on
> hardware.
Applied to controller/dwc for v6.14, thank you!
Krzysztof
> On 14 Jan 2025, at 3:47 AM, Namhyung Kim wrote:
>
> On Fri, Jan 10, 2025 at 03:07:30PM +0530, Athira Rajeev wrote:
>> perf lock contention returns zero exit value even if the lock contention
>> BPF setup failed.
>>
>> # ./perf lock con -b true
>> libbpf: kernel BTF is missing at '/sys/ker
> -Original Message-
> From: Jakub Kicinski
> Sent: 2025年1月16日 10:41
> To: Wei Fang
> Cc: Claudiu Manoil ; Vladimir Oltean
> ; Clark Wang ;
> andrew+net...@lunn.ch; da...@davemloft.net; eduma...@google.com;
> pab...@redhat.com; christophe.le...@csgroup.eu; net...@vger.kernel.org;
> linux-
This series adds UACCESS validation for PPC32. It includes
a dozen of changes to objtool core.
It applies on top of series "Cleanup/Optimise KUAP (v3)"
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=363368&state=*
It is almost mature, performs code analysis for all PPC32.
In this
At the time being, the end of a switch table can only be known
once the start of the following switch table has ben located.
This is a problem when switch tables are nested because until the first
switch table is properly added, the second one cannot be located as a
the backward walk will abut on
Cross build for powerpc/32 on x86_64 leads to:
CC init/main.o
init/main.o: warning: objtool: early_randomize_kstack_offset+0xf0: Unknown
annotation type: 134217728
init/main.o: warning: objtool: start_kernel+0x4a8: Unknown annotation type:
134217728
init/main.o: warning: objtool: do_one_i
Exclude sections named
.rodata.cst2
.rodata.cst4
.rodata.cst8
.rodata.cst16
as they won't contain switch tables.
Signed-off-by: Christophe Leroy
---
tools/objtool/check.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
i
This commit is copied from commit bfb1a7c91fb7 ("x86/bug: Merge
annotate_reachable() into _BUG_FLAGS() asm")
'twi 31,0,0' is a BUG instruction, which is by default a dead end.
But the same instruction is used for WARNINGs and the execution
resumes with the following instruction. Mark it reachable
When walking backward to find the base address of a switch table,
also take into account conditionnal branches and dynamic jumps from
a previous switch table.
To avoid mis-routing, break when stumbling on a function return.
Signed-off-by: Christophe Leroy
---
tools/objtool/check.c | 8 ++--
On powerpc, switch tables are relative, than means the address of the
table is added to the value of the entry in order to get the pointed
address: (r10 is the table address, r4 the index in the table)
lis r10,0 <== Load r10 with upper part of .rodata address
R_PPC_
struct jump_entry {
s32 code;
s32 target;
long key;
};
It means that the size of the third argument depends on
whether we are building a 32 bits or 64 bits kernel.
Therefore JUMP_ENTRY_SIZE must depend on elf_class_addrsize(elf).
To
On x86, UACCESS is controlled by two instructions: STAC and CLAC.
STAC instruction enables UACCESS while CLAC disables UACCESS.
This is simple enough for objtool to locate UACCESS enable and
disable.
But on powerpc it is a bit more complex, the same instruction is
used for enabling and disabling U
Supporting objtool on ASM files requires quite an effort.
Features like UACCESS validation don't require ASM files validation.
In order to allow architectures to enable objtool validation
without spending unnecessary effort on cleaning up ASM files,
provide an option to disable objtool validation
noreturns.h is a mix of x86 specific functions and more generic
core functions.
In preparation of inclusion of powerpc, split x86 functions out of
noreturns.h into arch/noreturns.h
Signed-off-by: Christophe Leroy
---
.../objtool/arch/x86/include/arch/noreturns.h | 20 +++
tools/
Those two functions loop over the instructions of a function.
Merge the two loops in order to ease enhancement of table end
in a following patch.
Signed-off-by: Christophe Leroy
---
tools/objtool/check.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/too
In order to implement UACCESS validation, objtool support
for powerpc needs to be enhanced to decode more instructions.
It also requires implementation of switch tables finding.
On PPC32 it is similar to x86, switch tables are anonymous in .rodata,
the difference is that the value is relative to i
A function can contain nested switch tables using different registers
as base address.
In order to avoid failure in tracking those switch tables, the register
containing the base address needs to be taken into account.
To do so, add a 5 bits field in struct instruction that will hold the
ID of th
A comment was introduced by commit 113d4bc90483 ("objtool: Fix
clang switch table edge case") and wrongly moved by
commit d871f7b5a6a2 ("objtool: Refactor jump table code to support
other architectures") without the piece of code added with the
comment in the original commit.
Fixes: d871f7b5a6a2 (
On Sun, Jan 12, 2025 at 02:39:02PM +0100, Krzysztof Kozlowski wrote:
> Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
> syscon_regmap_lookup_by_phandle() combined with getting the syscon
> argument. Except simpler code this annotates within one line that given
> phandle has arg
On 1/15/25 11:40 PM, Joe Lawrence wrote:
> On Tue, Jan 14, 2025 at 08:01:44PM +0530, Madhavan Srinivasan wrote:
>> Some arch configs (like ppc64) enable CONFIG_PRINTK_CALLER, which
>> adds the caller id as part of the dmesg. Due to this, even though
>> the expected vs observed are same, end test
On Mon, Jan 13, 2025 at 07:11:40PM +0200, Dmitry V. Levin wrote:
> These functions are going to be needed on all HAVE_ARCH_TRACEHOOK
> architectures to implement PTRACE_SET_SYSCALL_INFO API.
>
> This partially reverts commit 7962c2eddbfe ("arch: remove unused
> function syscall_set_arguments()") b
On Mon, Jan 13, 2025 at 07:11:51PM +0200, Dmitry V. Levin wrote:
> Similar to syscall_set_arguments() that complements
> syscall_get_arguments(), introduce syscall_set_nr()
> that complements syscall_get_nr().
>
> syscall_set_nr() is going to be needed along with
> syscall_set_arguments() on all H
> On Mon, 13 Jan 2025 16:22:39 +0800 Wei Fang wrote:
> > Add Receive side scaling (RSS) support for i.MX95 ENETC PF to improve the
> > network performance and balance the CPU loading. In addition, since both
> > ENETC v1 and ENETC v4 only support the toeplitz algorithm, so a check for
> > hfunc was
Most functions have an unconditional return at the end, like
this one:
:
0: 81 22 04 d0 lwz r9,1232(r2)
4: 38 60 00 00 li r3,0
8: 2c 09 00 00 cmpwi r9,0
c: 4d 82 00 20 beqlr <== Conditional re
On Fri, Jan 10, 2025 at 06:40:27PM +, Brendan Jackman wrote:
> Subject: Re: [PATCH RFC v2 01/29] mm: asi: Make some utility functions
> noinstr compatible
The tip tree preferred format for patch subject prefixes is
'subsys/component:', e.g. 'x86/apic:', 'x86/mm/fault:', 'sched/fair:',
'genirq
On Thu, 16 Jan 2025 02:24:10 + Wei Fang wrote:
> > Why create full ops for something this trivial?
>
> We add enetc_pf_hw_ops to implement different hardware ops
> for different chips. So that they can be called in common functions.
> Although the change is minor, it is consistent with the o
Le 15/01/2025 à 23:42, Christophe Leroy a écrit :
This series adds UACCESS validation for PPC32. It includes
a dozen of changes to objtool core.
It applies on top of series "Cleanup/Optimise KUAP (v3)"
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=363368&state=*
I forgot to
This adds all symbols required for use case like
livepatching. Distros already enable this config
and enabling this increases build time by 3%
(in a power9 128 cpu setup) and almost no size
changes for vmlinux.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/configs/powernv_defconfig | 1 +
On Fri, Jan 10, 2025 at 03:16:08PM +0100, Joel Granados wrote:
[...]
> diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c
> index 7a35c82976e0..9453f0c26f2a 100644
> --- a/drivers/hv/hv_common.c
> +++ b/drivers/hv/hv_common.c
> @@ -141,7 +141,7 @@ static int sysctl_record_panic_msg = 1;
>
Introduce a new PMU named 'kvm-hv' to report Book3s kvm-hv specific
performance counters. This will expose KVM-HV specific performance
attributes to user-space via kernel's PMU infrastructure and would enable
users to monitor active kvm-hv based guests.
The patch creates necessary scaffolding to f
Add support for adding and parsing Hostwide elements to the
Guest-state-buffer data structure used in apiv2. These elements are used to
share meta-information pertaining to entire L1-Lpar and this
meta-information is maintained by L0-PowerVM hypervisor. Example of this
include the amount of the pag
Update 'test-guest-state-buffer.c' to add two new KUNIT test cases for
validating correctness of changes to Guest-state-buffer management
infrastructure for adding support for Hostwide GSB elements.
The newly introduced test test_gs_hostwide_msg() checks if the Hostwide
elements can be set and par
Changes from V1
Link: https://lore.kernel.org/all/20241222140247.174998-1-vaib...@linux.ibm.com
* Fixed an issue preventing loading of kvm-hv on PowerNV [Gautam]
* Improved the error handling of GSB callback hostwide_fill_info() [Gautam]
* Tweaks to documentation of Hostwide counters [Gautam]
* Pr
Update 'book3s_hv_pmu.c' to add five new perf-events mapped to the five
Hostwide counters. Since these newly introduced perf events are at system
wide scope and can be read from any L1-Lpar CPU, 'kvmppv_pmu's scope and
capabilities are updated appropriately.
Also introduce two new helpers. First i
Implement and setup necessary structures to send a prepolulated
Guest-State-Buffer(GSB) requesting hostwide counters to L0-PowerVM and have
the returned GSB holding the values of these counters parsed. This is done
via existing GSB implementation and with the newly added support of
Hostwide element
Update kvm-nested APIv2 documentation to include five new
Guest-State-Elements to fetch the hostwide counters. These counters are
per L1-Lpar and indicate the amount of Heap/Page-table memory allocated,
available and Page-table memory reclaimed for all L2-Guests active
instances
Cc: linux-...@vger
The PE Reset State "0" returned by RTAS calls
"ibm_read_slot_reset_[state|state2]" indicates that the reset is
deactivated and the PE is in a state where MMIO and DMA are allowed.
However, the current implementation of "pseries_eeh_get_state()" does
not reflect this, causing drivers to incorrectly
On 13/01/25 1:28 pm, Athira Rajeev wrote:
Some of the tests depends on pvr value to choose
the event. Example:
- event_alternatives_tests_p10: alternative event depends
on registered PMU driver which is based on pvr
- generic_events_valid_test varies based on platform
- bhrb_filter_map_test: ag
On Fri, Jan 10 2025 at 15:16, Joel Granados wrote:
> sed:
> sed --in-place \
> -e "s/struct ctl_table .table = &uts_kern/const struct ctl_table *table
> = \&uts_kern/" \
> kernel/utsname_sysctl.c
>
> Reviewed-by: Song Liu
> Acked-by: Steven Rostedt (Google) # for kernel/trace/
>
Hi,
On Wed, Jan 15, 2025 at 02:47:58PM +0900, Akihiko Odaki wrote:
> elf.h had a comment saying:
> > Notes used in ET_CORE. Architectures export some of the arch register
> > sets using the corresponding note types via the PTRACE_GETREGSET and
> > PTRACE_SETREGSET requests.
> > The note name for t
On Tue, Jan 14, 2025 at 08:01:44PM +0530, Madhavan Srinivasan wrote:
> Some arch configs (like ppc64) enable CONFIG_PRINTK_CALLER, which
> adds the caller id as part of the dmesg. Due to this, even though
> the expected vs observed are same, end testcase results are failed.
>
> -% insmod test_mod
On Fri, Jan 10, 2025 at 03:16:08PM +0100, Joel Granados wrote:
> Add the const qualifier to all the ctl_tables in the tree except for
> watchdog_hardlockup_sysctl, memory_allocation_profiling_sysctls,
> loadpin_sysctl_table and the ones calling register_net_sysctl (./net,
> drivers/inifiniband dirs
On Mon, 13 Jan 2025 16:22:39 +0800 Wei Fang wrote:
> Add Receive side scaling (RSS) support for i.MX95 ENETC PF to improve the
> network performance and balance the CPU loading. In addition, since both
> ENETC v1 and ENETC v4 only support the toeplitz algorithm, so a check for
> hfunc was added.
T
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