On Tue 11-07-17 12:32:57, Ram Pai wrote:
> On Tue, Jul 11, 2017 at 04:52:46PM +0200, Michal Hocko wrote:
> > On Wed 05-07-17 14:21:37, Ram Pai wrote:
> > > Memory protection keys enable applications to protect its
> > > address space from inadvertent access or corruption from
> > > itself.
> > >
>
On Wed 12-07-17 09:23:37, Michal Hocko wrote:
> On Tue 11-07-17 12:32:57, Ram Pai wrote:
[...]
> > Ideally the MMU looks at the PTE for keys, in order to enforce
> > protection. This is the case with x86 and is the case with power9 Radix
> > page table. Hence the keys have to be programmed into the
Benjamin Herrenschmidt writes:
> On POWER9 and bad paste instruction (targeting the wrong memory
> type) or an invalid opcode in an AMO (atomic memory operation)
> will result in specific DSISR bits to be set.
>
> We currently don't understand those bits and thus just "hang"
> the process taking
This serie makes the PINning of ITLBs optional in the 8xx
in order to allow STRICT_KERNEL_RWX to work properly
Christophe Leroy (7):
powerpc/8xx: Ensures RAM mapped with LTLB is seen as block mapped on
8xx.
powerpc/8xx: Remove macro that checks kernel address
powerpc/32: Avoid risk of un
On the 8xx, the RAM mapped with LTLBs must be seen as block mapped,
just like areas mapped with BATs on standard PPC32.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/8xx_mmu.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arc
The macro to check if an address is a kernel address or not is
not used anymore in DTLBmiss handler. It is used in ITLB miss handler
and in DTLB error handler. DTLB error handler is not a hot path, it
doesn't need such optimisation.
In order to simplify a following patch which will rework ITLB mis
By default, the 8xx pins an ITLB on the first 8M of memory in order
to avoid any ITLB miss on kernel code.
However, with some debug functions like DEBUG_PAGEALLOC and
DEBUG_RODATA, pinning TLBs is contradictory.
In order to avoid any ITLB miss in a critical section without pinning
TLBs, we have to
As stated in a comment in head_8xx.S, today we "Always pin the first
8 MB ITLB to prevent ITLB misses while mucking around with SRR0/SRR1
in asm".
This issue has just been cleared by the preceding patch, therefore
we can make this pinning optional (on by default) and independent
of DATA pinning.
Pinning TLBs bypasses STRICT_KERNEL_RWX or DEBUG_PAGEALLOC protections
so it should only be allowed when those are not selected
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconf
setup_initial_memory_limit() is only called during init.
mmu_patch_cmp_limit() is only called from 8xx_mmu.c
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/8xx_mmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_m
This reduces the DTLB miss handler hot path (user address path)
by one instruction by preserving r10.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerp
Hello,
On Wed, 12 Jul 2017 00:00:57 +0530
Hari Bathini wrote:
> Hi Michal,
>
>
> Thanks for the review..
>
>
> On Monday 26 June 2017 05:45 PM, Michal Suchánek wrote:
> > Hello,
> >
> > On Tue, 20 Jun 2017 21:14:08 +0530
> > Hari Bathini wrote:
> >
> I would prefer documenting over a com
Sukadev Bhattiprolu writes:
> Hi Arnaldo,
>
> Please pull the JSON files for POWER9 PMU events.
>
> The following changes since commit 07d306c838c5c30196619baae36107d0615e459b:
>
> Merge git://www.linux-watchdog.org/linux-watchdog (2017-07-11 09:59:37
> -0700)
>
> are available in the git repo
On Wednesday 12 July 2017 05:01 PM, msuchanek wrote:
Hello,
On Wed, 12 Jul 2017 00:00:57 +0530
Hari Bathini wrote:
Hi Michal,
Thanks for the review..
On Monday 26 June 2017 05:45 PM, Michal Suchánek wrote:
Hello,
On Tue, 20 Jun 2017 21:14:08 +0530
Hari Bathini wrote:
I would pref
Em Wed, Jul 12, 2017 at 10:09:12PM +1000, Michael Ellerman escreveu:
> Sukadev Bhattiprolu writes:
> > Please pull the JSON files for POWER9 PMU events.
> > perf vendor events: Add POWER9 PMU events
> > perf vendor events: Add POWER9 PVRs to mapfile
> I think the PVRs need work.
>
Virtual time base(vtb) is a register which increases only in guest.
Any exit from guest to host will stop the vtb(saved and restored by kvm).
But if there is an IO causes guest exits to host, the guest's watchdog
(watchdog_timer_fn -> is_softlockup -> get_timestamp -> running_clock)
needs to also i
gup_hugepte() checks if pages are present and readable, and
when 'write' is set, also checks if the pages are writable.
Initially this was done by checking if _PAGE_PRESENT and
_PAGE_READ were set. In addition, _PAGE_WRITE was verified for write
accesses.
The problem is that we have to handle th
Em 2017-07-05 13:03, victora escreveu:
Em 2017-07-05 01:26, Aneesh Kumar K.V escreveu:
On Tuesday 04 July 2017 01:35 AM, Victor Aoqui wrote:
Implemented default hugepage size verification (default_hugepagesz=)
in order to allow allocation of defined number of pages (hugepages=)
only for support
Arnaldo Carvalho de Melo [a...@kernel.org] wrote:
> Em Wed, Jul 12, 2017 at 10:09:12PM +1000, Michael Ellerman escreveu:
> > Sukadev Bhattiprolu writes:
> > > Please pull the JSON files for POWER9 PMU events.
>
> > > perf vendor events: Add POWER9 PMU events
> > > perf vendor events:
Em Wed, Jul 12, 2017 at 09:40:08AM -0700, Sukadev Bhattiprolu escreveu:
> Arnaldo Carvalho de Melo [a...@kernel.org] wrote:
> > Em Wed, Jul 12, 2017 at 10:09:12PM +1000, Michael Ellerman escreveu:
> > > So for starters you should probably drop that one and add 0x004e1200 and
> > > 0x004e0200.
> Y
On Tue, Jul 11, 2017 at 10:33:09AM -0700, Dave Hansen wrote:
> On 07/05/2017 02:22 PM, Ram Pai wrote:
> > Abstracted out the arch specific code into the header file, and
> > added powerpc specific changes.
> >
> > a) added 4k-backed hpte, memory allocator, powerpc specific.
> > b) added three test
On Tue, Jul 11, 2017 at 11:10:46AM -0700, Dave Hansen wrote:
> On 07/05/2017 02:21 PM, Ram Pai wrote:
> > Currently there are only 4bits in the vma flags to support 16 keys
> > on x86. powerpc supports 32 keys, which needs 5bits. This patch
> > introduces an addition bit in the vma flags.
> >
> >
On Mon, 2017-06-26 at 20:08 +0200, Frederic Barrat wrote:
> + if (desc & OPAL_PCI_P2P_ENABLE) {
> + pe_init->p2p_initiator_count++;
> + } else {
> + if (pe_init->p2p_initiator_count > 0) {
> + pe_init->p2p_initiator_count--;
> +
On Wed, 2017-07-12 at 15:23 -0700, Ram Pai wrote:
> Just copying over makes checkpatch.pl unhappy. It exceeds 80 columns.
Which is fine to ignore in a case like that where you remain consistent
with the existing code.
Ben.
On Wed, 2017-07-12 at 23:01 +0800, Jia He wrote:
> Virtual time base(vtb) is a register which increases only in guest.
> Any exit from guest to host will stop the vtb(saved and restored by kvm).
> But if there is an IO causes guest exits to host, the guest's watchdog
> (watchdog_timer_fn -> is_soft
On Wed, 2017-07-12 at 09:23 +0200, Michal Hocko wrote:
>
> >
> > Ideally the MMU looks at the PTE for keys, in order to enforce
> > protection. This is the case with x86 and is the case with power9 Radix
> > page table. Hence the keys have to be programmed into the PTE.
>
> But x86 doesn't updat
Le 12/07/2017 à 17:39, Benjamin Herrenschmidt a écrit :
On Mon, 2017-06-26 at 20:08 +0200, Frederic Barrat wrote:
+ if (desc & OPAL_PCI_P2P_ENABLE) {
+ pe_init->p2p_initiator_count++;
+ } else {
+ if (pe_init->p2p_initiator_count > 0) {
+
On Wed, 2017-07-12 at 18:01 -0500, Frederic Barrat wrote:
> > So you have the initiator refcounting in Linux and the target
> > refcounting in OPAL ... any reason for that ?
>
> The initiator refcount is per PE and skiboot doesn't track PEs. Also
> when the initiator refcount falls back to 0, we
On Tue, Jul 11, 2017 at 7:34 PM, Daniel Axtens wrote:
> Hi Matt,
>
>> Currently ppc_md.get_random_seed uses the powernv_get_random_long function.
>> A guest calling this function would have to go through the hypervisor. The
>> 'darn' instruction, introduced in POWER9, allows us to bypass this by
>
Matt Brown writes:
> On Tue, Jul 11, 2017 at 7:34 PM, Daniel Axtens wrote:
>>> @@ -67,6 +69,21 @@ int powernv_get_random_real_mode(unsigned long *v)
>>> return 1;
>>> }
>>>
>>> +int powernv_get_random_darn(unsigned long *v)
>>
>> This is only referenced in this file so it should probably b
This patch adds emulation of the cmpb instruction, enabling xmon to
emulate this instruction.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 24
1 file changed, 24 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 33117f8..f3
This adds emulations for the popcntb, popcntw, and popcntd instructions.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index f3e9ba8..cf69987
This adds emulation for the bpermd instruction.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index cf69987..603654d 100644
--- a/arch/powerpc/lib/sstep.c
+++
This add emulation for the prtyw and prtyd instructions.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 58 +++-
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 603654d.
This add emulation for the isel instruction.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 3228783..bb0e301 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/
Arnaldo Carvalho de Melo writes:
> Em Wed, Jul 12, 2017 at 10:09:12PM +1000, Michael Ellerman escreveu:
>> Sukadev Bhattiprolu writes:
>> > Please pull the JSON files for POWER9 PMU events.
>
>> > perf vendor events: Add POWER9 PMU events
>> > perf vendor events: Add POWER9 PVRs to m
Sukadev Bhattiprolu writes:
...
>
> tools/perf/pmu-events/arch/powerpc/mapfile.csv | 3 +
> .../perf/pmu-events/arch/powerpc/power9/cache.json | 176 +
> .../arch/powerpc/power9/floating-point.json| 44 ++
> .../pmu-events/arch/powerpc/power9/frontend.json | 446 +++
>
On 13/07/17 13:25, Matt Brown wrote:
@@ -1049,6 +1066,13 @@ int analyse_instr(struct instruction_op *op, struct
pt_regs *regs,
do_cmp_unsigned(regs, val, val2, rd >> 2);
goto instr_done;
+ case 19173952: /* cmpb */
This looks wrong
On Thu 13-07-17 08:53:52, Benjamin Herrenschmidt wrote:
> On Wed, 2017-07-12 at 09:23 +0200, Michal Hocko wrote:
> >
> > >
> > > Ideally the MMU looks at the PTE for keys, in order to enforce
> > > protection. This is the case with x86 and is the case with power9 Radix
> > > page table. Hence the
On Thu, Jul 13, 2017 at 01:51:30PM +1000, Andrew Donnellan wrote:
> On 13/07/17 13:25, Matt Brown wrote:
> >@@ -1049,6 +1066,13 @@ int analyse_instr(struct instruction_op *op, struct
> >pt_regs *regs,
> > do_cmp_unsigned(regs, val, val2, rd >> 2);
> > goto i
On Thu, Jul 13, 2017 at 01:25:44PM +1000, Matt Brown wrote:
> +static nokprobe_inline void do_cmpb(struct pt_regs *regs, unsigned long v1,
> + unsigned long v2, int rd)
> +{
> + unsigned long out_val, mask;
> + int i;
> +
> + out_val = 0;
> + for (i = 0;
Hi Ben
I add some printk logs in watchdog_timer_fn in the guest
[ 16.025222] get_vtb=8236291881, get_tb=13756711357, get_timestamp=4
[ 20.025624] get_vtb=9745285807, get_tb=15804711283, get_timestamp=7
[ 24.025042] get_vtb=11518119641, get_tb=17852711085, get_timestamp=10
[ 28.024074] get_
42 matches
Mail list logo
