From: Xuelin Shi
adding unmap of sources and destinations while doing dequeue.
Signed-off-by: Xuelin Shi
---
drivers/dma/fsldma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 2209f75..aac85c3 100644
--- a/drivers/dma/fsldma.c
+++ b/dri
On 08/03/16 12:48, Ian Munsie wrote:
From: Ian Munsie
This adds an afu_driver_ops structure with event_pending and
deliver_event callbacks. An AFU driver such as cxlflash can fill these
out and associate it with a context to enable passing custom AFU
specific events to userspace.
The cxl drive
On 08/03/16 12:48, Ian Munsie wrote:
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU drivers to use, as they can easily
get back to any privat
On 03/08/2016 12:41 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2016-03-07 at 21:04 +0530, Aneesh Kumar K.V wrote:
>> Sebastian Andrzej Siewior writes:
>>
>> While you are there, can you also fix the wrong indentation on line
>> 423
>> ?
>
> .../...
>
> Also this looks like stable material no
hugepd_free() used __get_cpu_var() once. Nothing ensured that the code
accessing the variable did not migrate from one CPU to another and soon
this was noticed by Tiejun Chen in 94b09d755462 ("powerpc/hugetlb:
Replace __get_cpu_var with get_cpu_var"). So we had it fixed.
Christoph Lameter was doin
Hi Li,
On Tue, 2016-03-08 at 11:55 +0800, Li Zhang wrote:
> From: Li Zhang
>
> Parallel initialisation has been enabled for X86, boot time is
> improved greatly. On Power8, it is improved greatly for small
> memory. Here is the result from my test on Power8 platform:
>
> For 4GB memory: 57% is i
On Tue, Mar 08, 2016 at 06:33:57PM +1100, Balbir Singh wrote:
> Changelog v5:
> 1. Removed the mini-stack frame created for klp_return_helper.
> As a result of the mini-stack frame, function with > 8
> arguments could not be patched
Did you get my previous mails? Those func
On Mon, Mar 07, 2016 at 02:41:16PM +1100, Alexey Kardashevskiy wrote:
> This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
> and H_STUFF_TCE requests targeted an IOMMU TCE table used for VFIO
> without passing them to user space which saves time on switching
> to user space and bac
On Fri, Mar 04, 2016 at 08:22:22PM +0100, Torsten Duwe wrote:
> On Fri, Mar 04, 2016 at 07:16:57PM +0100, Torsten Duwe wrote:
> > On Fri, Mar 04, 2016 at 02:01:37PM +0100, Petr Mladek wrote:
> > >
> > > Do I understand it correctly that we could not patch functions that
> > > pass arguments on the
On Mon, 7 Mar 2016, Michael Ellerman wrote:
> On Fri, 2016-03-04 at 09:58 -0800, Hugh Dickins wrote:
> >
> > The alternative bisection was as unsatisfactory as the first:
> > again it fingered an irrelevant merge (rather than any commit
> > pulled in by that merge) as the bad commit.
> >
> > It s
On 03/08/2016 04:55 AM, Li Zhang wrote:
> From: Li Zhang
>
> This patch is based on Mel Gorman's old patch in the mailing list,
> https://lkml.org/lkml/2015/5/5/280 which is discussed but it is
> fixed with a completion to wait for all memory initialised in
> page_alloc_init_late(). It is to fix
On 08/03/16 21:45, Torsten Duwe wrote:
> On Tue, Mar 08, 2016 at 06:33:57PM +1100, Balbir Singh wrote:
>> Changelog v5:
>> 1. Removed the mini-stack frame created for klp_return_helper.
>> As a result of the mini-stack frame, function with > 8
>> arguments could not be patche
On 08/03/16 14:55, Li Zhang wrote:
> From: Li Zhang
>
> Uptream has supported page parallel initialisation for X86 and the
> boot time is improved greately. Some tests have been done for Power.
>
> Here is the result I have done with different memory size.
>
> * 4GB memory:
> boot time is as
On Wed, Mar 09, 2016 at 12:52:03AM +1100, Balbir Singh wrote:
>
> On 08/03/16 21:45, Torsten Duwe wrote:
> > To be fair, my last mail still was not 100% correct, but the conclusion
Wrote a correction to the correction. It should be clear now. Please nag me
if it isn't clear why klp_return_helper
On Tue 2016-03-08 18:33:57, Balbir Singh wrote:
> Changelog v5:
> 1. Removed the mini-stack frame created for klp_return_helper.
> As a result of the mini-stack frame, function with > 8
> arguments could not be patched
> 2. Removed camel casing in the comments
I teste
On 3/4/2016 3:55 PM, Uma Krishnan wrote:
From: "Manoj N. Kumar"
The calls to pci_request_regions(), pci_resource_start(),
pci_set_dma_mask(), pci_set_master() and pci_save_state() are all
unnecessary for the IBM CXL flash adapter since data buffers
are not required to be mapped to the device's
On 3/4/2016 3:55 PM, Uma Krishnan wrote:
From: "Matthew R. Ochs"
The cxlflash_disk_attach() routine currently uses a cascading error
gate strategy for its error cleanup path. While this strategy is
commonly used to handle cleanup scenarios, it is too restrictive when
function callouts need to b
On 3/4/2016 3:55 PM, Uma Krishnan wrote:
From: "Matthew R. Ochs"
Presently, context information structures are allocated and
initialized in the same routine, create_context(). This imposes
an ordering restriction such that all pieces of information needed
to initialize a context must be known b
On 3/4/2016 3:55 PM, Uma Krishnan wrote:
From: "Manoj N. Kumar"
When switching to the internal LUN defined on the
IBM CXL flash adapter, there is an unnecessary
scan occurring on the second port. This scan leads
to the following extra lines in the log:
Dec 17 10:09:00 tul83p1 kernel: [ 3708.56
On 3/4/2016 3:55 PM, Uma Krishnan wrote:
From: "Manoj N. Kumar"
With the current value of cmd_per_lun at 16, the throughput
over a single adapter is limited to around 150kIOPS.
Increase the value of cmd_per_lun to 256 to improve
throughput. With this change a single adapter is able to
attain c
cmm_mem_going_offline is (only) called from cmm_memory_cb(), which
sends the return value through notifier_from_errno(). The latter
expects 0 or -errno (notifier_to_errno(notifier_from_errno(x)) is 0
for any x >= 0, so passing a positive value cannot make sense). Hence
negate ENOMEM.
Signed-off-by
On Thu, 3 Mar 2016 17:52:01 +0100
Petr Mladek wrote:
> From: Balbir Singh
>
> Changelog v4:
> 1. Renamed klp_matchaddr() to klp_get_ftrace_location()
> and used it just to convert the function address.
> 2. Synced klp_write_module_reloc() with s390(); made it
> in
On Tue, Mar 08, 2016 at 06:42:56PM +1100, Andrew Donnellan wrote:
>On 09/02/16 10:57, Andrew Donnellan wrote:
>>It is a fix - I'm a bit hazy on the details now but IIRC, Daniel Axtens
>>and I encountered this when doing some cxl debugging, though I think we
>>decided not to tag this for stable sinc
This dependency led to kconfig errors when MTD_NAND_FSL_ELBC was
enabled, which selects FSL_LBC, in the absence of FSL_SOC, as reported
in http://patchwork.ozlabs.org/patch/564405/
It was originally suggested to add an FSL_SOC dependency to
MTD_NAND_FSL_ELBC, but the FSL_SOC symbol has been a grow
On Fri, Jan 08, 2016 at 10:46:53AM +0800, Zhao Qiang wrote:
> Add maxim ds26522 document to
> Documentation/devicetree/bindings/tdm/maxim,ds26522.txt
>
> Signed-off-by: Zhao Qiang
> Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/tdm/maxim,ds26522.txt | 13 +
> 1 fil
On Fri, Jan 22, 2016 at 04:19:07PM +0800, Dongsheng Wang wrote:
> +void p1022ds_reset_pcie_slot(void)
> +{
> + if (px_ctl_altacc_flag)
> + indirect_access_pixis_reset_pcie_slot();
> + else
> + direct_access_pixis_reset_pcie_slot();
> +}
This function is not called a
On Thu, Jan 28, 2016 at 06:47:39PM +0530, Ashish kumar wrote:
> B4860 has 1 PPC core cluster and 3 DSP core clusters.
> Similarly B4420 has 1 PPC core cluster and 1 DSP core cluster.
>
> Each DSP core cluster consists of 2 SC3900 cores and a shared L2 cache.
>
> Add DSP clusters for B4420
> The L
On Mon, 2016-02-29 at 20:03 +0100, luigi burdo wrote:
> Hi all,
> sorry for this email but i need to ask to Alexander Graf and Michael
> Ellerman if will be possible have kvm and kvm-pr for the Freescale/Nix P5020
> cpu .
KVM for e5500 uses hardware hypervisor features. PR-mode KVM is not
suppo
On Tue, 2016-03-08 at 01:16 +, Qiang Zhao wrote:
> On Tue, Mar 08, 2016 at 1:28AM, Scott Wood wrote:
> > -Original Message-
> > From: Scott Wood [mailto:o...@buserror.net]
> > Sent: Tuesday, March 08, 2016 1:28 AM
> > To: Qiang Zhao ; Rob Herring
> > Cc: Yang-Leo Li ; Xiaobo Xie ;
> >
On Tue, 2016-03-01 at 15:41 +, Nora Björklund wrote:
> Hi,
>
> I was working on a p2041rdb target not so long ago and needed to use
> the gpio pins (described in detail in the p2041 reference manual),
> these are visible on the p2041 fact sheet [1]. The pins are connected
> to a gpio expander,
On Wed, 2016-03-09 at 01:27 +0100, luigi burdo wrote:
> Hi Scott, thanks for the reply,
> about: I don't know what you mean by "working only on emb side".
> thru qemu 2.5 i can use only ppcemb as kvm not ppc64 or ppc
Oh, you mean the QEMU target... "ppc64" should work.
> Dont have the Kvm-pr is
Hi Scott, thanks for the reply,about: I don't know what you mean by "working
only on emb side".thru qemu 2.5 i can use only ppcemb as kvm not ppc64 or ppc
Dont have the Kvm-pr is a really unhappy news, it means we will not have the
opportunity to run for example Mol-kvm on this machine.
about:K
Add uqe_serial document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
Signed-off-by: Zhao Qiang
---
Changes for v2
- modify tx/rx-clock-name specification
Changes for v3
- NA
Changes for v4
- drop device_type
- modify to SoC specific compa
add qe node to t104xrdb.dtsi
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
Changes for v4
- rebase
Changes for v5
- rebase
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 38 +
1 file changed, 38 insertion
Add ucc hdlc document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
Signed-off-by: Zhao Qiang
Acked-by: Rob Herring
---
Changes for v2
- use ucc-hdlc instead of ucc_hdlc
- add more information to properties.
Changes for v3
- use fsl,tx-timeslot-mask
add qe node to t104xd4rdb.dtsi and t1040si-post.dtsi.
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
Changes for v4
- rebase
Changes for v5
- rebase
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 45 +
arc
New bindings use "fsl,t1040-ucc-uart" as the compatible for qe-uart.
So add it.
Signed-off-by: Zhao Qiang
---
drivers/tty/serial/ucc_uart.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 1a7dc3c..481eb29 100644
--- a/dri
On Tue, Mar 8, 2016 at 5:36 PM, Michael Ellerman wrote:
> Hi Li,
>
> On Tue, 2016-03-08 at 11:55 +0800, Li Zhang wrote:
>
>> From: Li Zhang
>>
>> Parallel initialisation has been enabled for X86, boot time is
>> improved greatly. On Power8, it is improved greatly for small
>> memory. Here is the
> "Uma" == Uma Krishnan writes:
Uma> The first 5 patches of this series contain fixes to support the
Uma> cxlflash driver in a PowerVM guest. For the cxlflash driver to be
Uma> functional in a PowerVM guest, a corresponding set of cxl patches
Uma> (currently being upstreamed) is required. Not
cpm_qe is supported on both powerpc and arm.
and the QE code has been moved from arch/powerpc into
drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl
to soc/fsl
Signed-off-by: Zhao Qiang
Acked-by: Rob Herring
---
Changes for v3
- NA
Changes for v4
- NA
Changes for v5
On 09/03/16 03:02, Petr Mladek wrote:
> On Tue 2016-03-08 18:33:57, Balbir Singh wrote:
>> Changelog v5:
>> 1. Removed the mini-stack frame created for klp_return_helper.
>> As a result of the mini-stack frame, function with > 8
>> arguments could not be patched
>> 2. Re
On 09/03/16 02:34, Torsten Duwe wrote:
> On Wed, Mar 09, 2016 at 12:52:03AM +1100, Balbir Singh wrote:
>> On 08/03/16 21:45, Torsten Duwe wrote:
>>> To be fair, my last mail still was not 100% correct, but the conclusion
> Wrote a correction to the correction. It should be clear now. Please nag m
add qe node to t104xqds.dtsi
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
Changes for v4
- rebase
Changes for v5
- rebase
arch/powerpc/boot/dts/fsl/t104xqds.dtsi | 38 +
1 file changed, 38 insertion
Add IC, SI and SIRAM document of QE to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
Signed-off-by: Zhao Qiang
Acked-by: Rob Herring
---
changes for v2
- Add interrupt-controller in Required properties
- delete address-cells and size-cells for qe-si and qe-siram
Cha
On Tue, Mar 8, 2016 at 10:45 PM, Balbir Singh wrote:
>
>
> On 08/03/16 14:55, Li Zhang wrote:
>> From: Li Zhang
>>
>> Uptream has supported page parallel initialisation for X86 and the
>> boot time is improved greately. Some tests have been done for Power.
>>
>> Here is the result I have done wit
On 09/03/16 15:17, Li Zhang wrote:
> On Tue, Mar 8, 2016 at 10:45 PM, Balbir Singh wrote:
>>
>> On 08/03/16 14:55, Li Zhang wrote:
>>> From: Li Zhang
>>>
>>> Uptream has supported page parallel initialisation for X86 and the
>>> boot time is improved greately. Some tests have been done for Powe
On Wed, Mar 9, 2016 at 12:28 PM, Balbir Singh wrote:
>
>
> On 09/03/16 15:17, Li Zhang wrote:
>> On Tue, Mar 8, 2016 at 10:45 PM, Balbir Singh wrote:
>>>
>>> On 08/03/16 14:55, Li Zhang wrote:
From: Li Zhang
Uptream has supported page parallel initialisation for X86 and the
b
On Mon, Mar 07, 2016 at 02:41:17PM +1100, Alexey Kardashevskiy wrote:
> sPAPR TCE IOMMU is para-virtualized and the guest does map/unmap
> via hypercalls which take a logical bus id (LIOBN) as a target IOMMU
> identifier. LIOBNs are made up, advertised to guest systems and
> linked to IOMMU groups
On Fri, 2016-04-03 at 11:26:36 UTC, Frederic Barrat wrote:
> From: Christophe Lombard
>
> The new of.c file contains code to parse the device tree to find out
> about cxl adapters and AFUs.
>
> guest.c implements the guest-specific callbacks for the backend API.
...
> diff --git a/drivers/misc/c
IBM POWER8 NVlink systems contain usual Tesla K40-ish GPUs but also
contain a couple of really fast links between GPU and CPU. These links
are exposed to the userspace by the OPAL firmware as bridges.
In order to make these links work when GPU is passed to the guest,
these bridges need to be passed
As in fact pnv_pci_ioda2_tce_invalidate_entire() invalidates TCEs for
the specific PE rather than the entire cache, rename it to
pnv_pci_ioda2_tce_invalidate_pe(). In later patches we will add
a proper pnv_pci_ioda2_tce_invalidate_entire().
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/pl
This uses the page size from iommu_table instead of hard-coded 4K.
This should cause no change in behavior.
While we are here, move bits around to prepare for further rework
which will define and use iommu_table_group_ops.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/n
We are going to have multiple different types of PHB on the same system
with POWER8 + NVLink and PHBs will have different IOMMU ops. However
we only really care about one callback - create_table - so we can
relax the compatibility check here.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/
IBM POWER8 NVlink systems contain usual Tesla K40-ish GPUs but also
contain a couple of really fast links between GPU and CPU. These links
are exposed to the userspace by the OPAL firmware as bridges.
The device tree has references from GPU to NPU and vice versa via
"ibm,npu" and "ibm,gpu" properti
NPU devices have their own TVT which means they are isolated and can be
passed to the userspace via VFIO. The first step is to create an IOMMU
group and attach devices there so does the patch.
This adds a helper to npu-dma.c which gets GPU from the NPU's pdev and
then walks through all devices on
The pnv_ioda_pe struct keeps an array of peers. At the moment it is only
used to link GPU and NPU for 2 purposes:
1. Access NPU _quickly_ when configuring DMA for GPU - this was addressed
in the previos patch by removing use of it as DMA setup is not what
the kernel would constantly do.
2. Invali
This replaces magic constants for TCE Kill IODA2 register with macros.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/
NPU devices are quite specific, in fact they represent side DMA channel
of a GPU device. The GPU/NPU driver never actually configures DMA
for NPU devices, instead it relies on the platform code to propagate
DMA setup to NPU devices when a main GPU device is being configured.
When GPU is being set u
NPU PHB TCE Kill register is exactly the same as in the rest of POWER8
so let's reuse the existing code for NPU. The only bit missing is
a helper to reset the entire TCE cache so this moves such a helper
from NPU code and renames it.
Since pnv_npu_tce_invalidate() does really invalidate the entire
On Tue, Mar 08, 2016 at 08:59:12AM +0100, Alessio Igor Bogani wrote:
> The mtmsr() function hangs during restart. Make reboot works on
> MVME5100 removing that function call.
> ---
> arch/powerpc/platforms/embedded6xx/mvme5100.c | 2 --
> 1 file changed, 2 deletions(-)
Missing signoff
Do you kno
The previous revision was nacked by Torsten, but compared to the alternatives
at hand I think we should test this approach. Ideally we want all the complexity
of live-patching in the live-patching code and not in the patch. The other
option
is to accept v4 and document the limitation to patch wri
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