IBM POWER8 NVlink systems contain usual Tesla K40-ish GPUs but also contain a couple of really fast links between GPU and CPU. These links are exposed to the userspace by the OPAL firmware as bridges. In order to make these links work when GPU is passed to the guest, these bridges need to be passed as well; otherwise performance will degrade. More details are in 10/10.
This reworks the existing NPU support in the powernv platform and adds VFIO support on top of that. This was tested on POWER8NVL platform. pvr=0x004c0100. Please comment. Thanks. Alexey Kardashevskiy (10): vfio/spapr: Relax the IOMMU compatibility check powerpc/powernv: Rename pnv_pci_ioda2_tce_invalidate_entire powerpc/powernv: Define TCE Kill flags powerpc/powernv/npu: TCE Kill helpers cleanup powerpc/powernv/npu: Use the correct IOMMU page size powerpc/powernv/npu: Simplify DMA setup powerpc/powernv/npu: Rework TCE Kill handling powerpc/powernv/npu: Add NPU devices to IOMMU group powerpc/powernv/ioda2: Export some helpers powerpc/powernv/npu: Enable passing through via VFIO arch/powerpc/platforms/powernv/npu-dma.c | 387 ++++++++++++++++++------------ arch/powerpc/platforms/powernv/pci-ioda.c | 134 +++++------ arch/powerpc/platforms/powernv/pci.h | 32 +-- drivers/vfio/vfio_iommu_spapr_tce.c | 3 +- 4 files changed, 309 insertions(+), 247 deletions(-) -- 2.5.0.rc3 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
