On Mon, 2009-09-21 at 17:53 -0700, Prodyut Hazarika wrote:
>
> In the newer revs of 460EX/GT and 405EX, we have Interrupt coalescing
> both on Tx and Rx per channel (physical not virtual), which can be
> enabled/disabled per channel via UIC. The Tx/Rx Coalesce mappings are
> defined in the dts fil
Hi Ben,
> Well... the above is a HW limitation :-) IE. I was suggesting you fix
> the HW, but in the case where you already did and the current MAL in
> your SoC can indeed mask the interrupt per-channel, then that's great
> and we should definitely look into having the driver go back to a more
>
On Mon, 2009-09-21 at 17:28 -0700, prodyut hazarika wrote:
> > BTW. If you guys are ever going to do another change to MAL, please
> > please plase, add the -one- major missing feature that's causing all
> the
> > pain and complication in the current design: Add a per-channel
> interrupt
> > maskin
Hi Ben,
>
> BTW. If you guys are ever going to do another change to MAL, please
> please plase, add the -one- major missing feature that's causing all the
> pain and complication in the current design: Add a per-channel interrupt
> masking option.
>
> The lack of ability to mask the interrupt per
On Mon, 2009-09-21 at 17:05 -0700, Prodyut Hazarika wrote:
> Hi Ben,
> Thanks again for your comments.
>
> > Same goes with the SDR register definitions. Prefix them with the SOC
> > name but don't make them conditionally compiled.
>
> I will add the base address in the Device tree, and make all
On Mon, 2009-09-21 at 16:49 -0700, Prodyut Hazarika wrote:
> Hi Ben,
> Thanks for your comments.
>
>
> > What happens if we build a kernel that is supposed to boot with two
> > different variants of 405 or 440 ?
>
> We cannot build a kernel with H/W Interrupt coalescing other than in
> 405EX/460
Hi Ben,
Thanks again for your comments.
> Same goes with the SDR register definitions. Prefix them with the SOC
> name but don't make them conditionally compiled.
I will add the base address in the Device tree, and make all register
definitions based on offset from the base in the next version of
Hi Ben,
Thanks for your comments.
> What happens if we build a kernel that is supposed to boot with two
> different variants of 405 or 440 ?
We cannot build a kernel with H/W Interrupt coalescing other than in
405EX/460EX/GT.
This is controlled via KConfig (config IBM_NEW_EMAC_INTR_COALESCE
depe
On Mon, 2009-09-21 at 15:47 -0700, Prodyut Hazarika wrote:
> Support for Hardware Interrupt coalescing in MAL.
> Coalescing is supported on the newer revs of 460EX/GT and 405EX.
> The MAL driver falls back to EOB IRQ if coalescing not supported
>
> Signed-off-by: Prodyut Hazarika
> Acked-by: Vict
