Hi Ben, > Well... the above is a HW limitation :-) IE. I was suggesting you fix > the HW, but in the case where you already did and the current MAL in > your SoC can indeed mask the interrupt per-channel, then that's great > and we should definitely look into having the driver go back to a more > standard NAPI model on MALs that have that capability.
In the newer revs of 460EX/GT and 405EX, we have Interrupt coalescing both on Tx and Rx per channel (physical not virtual), which can be enabled/disabled per channel via UIC. The Tx/Rx Coalesce mappings are defined in the dts file. But in the older revs, there is only a global EOP_Int_Enable in the MAL configuration register. There can be a possible way even for older SoCs if we use the MAL descriptor I bit and not the global EOP_Int_Enable. But to turn on/off the channel, we will have to go and set/clear the I bit in whole of MAL descriptor ring for that channel. That might be really inefficient. What would you suggest? Thanks Prodyut _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
