On Thu, 2008-01-03 at 18:14 +0800, Arnd Bergmann wrote:
> After some more research, I noticed that the distinction between
> primary and secondary host bridges will go away _anyway_, so
> I guess we shouldn't worry about it too much.
>
> On powerpc64, we already don't care, as the
> arch/powerp
On Thu, 2008-01-03 at 16:14 +0800, Arnd Bergmann wrote:
> On Thursday 03 January 2008, Li Li wrote:
> > > * The detection method for the primary bus is somewhat fragile,
> > > because
> > > we depend on the order of the nodes in the device tree, which is
> not
On Wed, 2008-01-02 at 19:53 +0800, Arnd Bergmann wrote:
> On Wednesday 02 January 2008, Li Li wrote:
> > #ifdef CONFIG_PCI
> > - for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
> > - mpc83xx_add_bridge(np);
> > +
On Wed, 2008-01-02 at 23:23 +0800, Kumar Gala wrote:
>
> On Jan 2, 2008, at 5:16 AM, Li Li wrote:
>
> > * The MPC837x PCIE controller hardware resources and SerDes are
> > initiated in u-boot.
> > * Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pc
* The MPC837x PCIE controller hardware resources and SerDes are initiated in
u-boot.
* Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pci.c
* The MPC837x PCIE controller`s configure address bit field is uniqe:
bus number: bits 31-24
device number: bit
Initial the MPC837x PCIE controller.
Note that configue address bit field is not compatible with PCIE spec 10a.
Just map first 16M pci configure space which corresponding to a bus configure
space at boot.
Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
Makefile |
The MPC837x PCIE controller hardware resources are initiated in u-boot.
Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pci.c
The MPC837x PCIE controller`s configure address bit field is uniqe:
bus number: bits 31-24
device number: bits 23-19
ysKonnect card.
> - k
>
> >> -Original Message-
> >> From: Kumar Gala [mailto:[EMAIL PROTECTED]
> >> Sent: 2007年12月14日 13:45
> >> To: Li Tony
> >> Cc: Phillips Kim; [EMAIL PROTECTED]; linuxppc-dev
> >> Subject: Re: [PATCH 2/2] powerpc:
Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 14 ++
arch/powerpc/boot/dts/mpc8378_mds.dts |
Modified based on discussion in list.
1.Change the device node to pcie
2.Add PPC_83XX_PCI_PRIMARY flag
3.Rearrange the codes
The PCIE controller is initiated in u-boot.
Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 54 --
arch/powerpc/boot/
Yes. According to the PCI spec, a PCI device can request multi MSI
interrupts and require that interrupts are consecutive.
But it is ok if only allocate one to it.
Anyway, the hwirq should be allocated from bitmap instead of increment
by hand.
I will correct this and resend the patch.
- Tony
On
On Tue, 2007-12-04 at 05:03 +0800, Benjamin Herrenschmidt wrote:
>
> On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote:
> >
> > In IPIC, the 8 MSI interrupts is handled as level intrrupt.
> > I just provide a versatile in case it is changed.
>
> Level ? Are you sure
Hi Michael,
I emulate mpic to write this IPIC MSI routines. :)
> > diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > b/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > index 6048f1b..dbea34b 100644
> > --- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > +++ b/arch/powerpc/platforms/83xx/m
On Mon, 2007-12-03 at 09:52 +0800, David Gibson wrote:
> On Fri, Nov 30, 2007 at 11:48:39AM +0800, Li Li wrote:
> > The IPIC MSI is introduced on MPC837x chip.
> > Implements the IPIC MSI as two level interrupt controller.
> >
> > Signed-off-by: Tony Li <[EMAIL P
On Fri, 2007-11-30 at 22:57 +0800, Gala Kumar wrote:
>
> On Nov 30, 2007, at 3:37 AM, Li Li wrote:
>
> > On Fri, 2007-11-30 at 17:05 +0800, Gala Kumar wrote:
> >>>>> +
> >>>>> + [EMAIL PROTECTED] {
> >>
On Fri, 2007-11-30 at 17:05 +0800, Gala Kumar wrote:
> >>> +
> >>> + [EMAIL PROTECTED] {
> >>
> >> I agree w/Olof. This should be [EMAIL PROTECTED]
> >>>
> >>> + interrupt-map-mask = ;
> >>> + msi-available-ranges = <43 4 51 52 56 57 58 59>;
> >>> + i
On Fri, 2007-11-30 at 15:37 +0800, Gala Kumar wrote:
>
> On Nov 29, 2007, at 9:45 PM, Li Li wrote:
>
> > The PCIE controller is initiated in u-boot.
> >
> > This patch is based on Leo`s mpc837xe patches.
> >
> >
> > Signed-off-by: Tony Li <[E
On Fri, 2007-11-30 at 12:14 +0800, Olof Johansson wrote:
> Hi,
>
> On Fri, Nov 30, 2007 at 11:45:34AM +0800, Li Li wrote:
>
> > + [EMAIL PROTECTED] {
>
> Why call it pci2@ (and pci3@ below)? They are clearly identifiable
> with
> their unit addresses anyway.
&
The IPIC MSI is introduced on MPC837x chip.
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 14 ++
arch/powerpc/boot/dts/mpc8378_mds.dts | 14 ++
arch/powerpc/boot/dts/mpc8379_mds.dts
The PCIE controller is initiated in u-boot.
This patch is based on Leo`s mpc837xe patches.
Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 56 --
arch/powerpc/boot/dts/mpc8378_mds.dts | 56 --
arch/powerpc/platforms/83xx/Kconfig
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