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> -Original Message-
> From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk]
> Sent: Thursday, March 07, 2013 7:04 PM
> To: Singh Sandeep-B37400
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> Aggrwal Poonam-B10812
> Subject: Re: [PATCH 1/4] Device tree
On Tue, Mar 12, 2013 at 03:48:02PM +0800, Jia Hongtao wrote:
> The MPIC chip with version 2.0 has a MSI errata (errata PIC1 of mpc8544),
> It causes that neither MSI nor MSI-X can work fine. This is a workaround
> to allow MSI-X to function properly.
You say "neither MSI nor MSI-X can work fine",
On Wed, Mar 06, 2013 at 11:40:13AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kvm/book3s_hv.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/power
On Wed, Mar 06, 2013 at 11:40:11AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We look at both the segment base page size and actual page size and store
> the pte-lp-encodings in an array per base page size.
>
> We also update all relevant functions to take actual page size arg
On Tue, Mar 12, 2013 at 05:38:49PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
> bits. Make the dependency explicit
>
> Signed-off-by: Aneesh Kumar K.V
Acked-by: Paul Mackerras
On Tue, Mar 12, 2013 at 05:38:51PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Now we use ESID_BITS of kernel address to build proto vsid. So rename
> USER_ESIT_BITS to ESID_BITS
>
> Signed-off-by: Aneesh Kumar K.V
Acked-by: Paul Mackerras
but it doesn't seem urgent.
Paul.
On Tue, Mar 12, 2013 at 05:38:50PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This patch change the kernel VSID range so that we limit VSID_BITS to 37.
> This enables us to support 64TB with 65 bit VA (37+28). Without this patch
> we have boot hangs on platforms that only suppo
On Wed, Mar 06, 2013 at 11:40:08AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We will use this later with THP changes to request for pmd table of double
> the size.
> THP code does PTE page allocation along with large page request and deposit
> them
> for later use. This is t
On Wed, Mar 06, 2013 at 11:40:12AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> As per ISA doc, we encode base and actual page size in the LP bits of
> PTE. The number of bit used to encode the page sizes depend on actual
> page size. ISA doc lists this as
>
>PTE LP act
On Tue, Mar 12, 2013 at 08:27:40PM +1100, Paul Mackerras wrote:
> On Tue, Mar 05, 2013 at 09:48:26PM -0800, Sukadev Bhattiprolu wrote:
> > Michael Ellerman [mich...@ellerman.id.au] wrote:
> > | I suspect Arnaldo was either waiting for an ACK from Ben, or was
> > | expecting Ben to take it?
> >
> >
Hi,
On Tue, Mar 12, 2013 at 10:51:51PM +1100, Anton Blanchard wrote:
> Commit 5ac47f7a6efb (powerpc: Relocate prom_init.c on 64bit) made
> prom_init.c position independent by manually relocating its entries
> in the TOC.
>
> We get the address of the TOC entries with the __prom_init_toc_start
> l
The Kconfig entry for QE_USB contains
default y if USB_GADGET_FSL_QE
But USB_GADGET_FSL_QE got removed in commit
193ab2a6070039e7ee2b9b9bebea754a7c52fd1b ("usb: gadget: allow multiple
gadgets to be built"). This default will therefor never be set and can
be removed.
Signed-off-by: Paul Bo
Hi,
On Tue, 12 Mar 2013 22:17:17 +0100
Matteo Facchinetti wrote:
> From: Matteo Facchinetti
>
> On platform mpc512x, PSC clock name registered by clk_register()
> (clock.c:703) has _mclk suffix.
> In mpc512x uart device driver, PSC clock name has _clk suffix.
>
> So change PSC clock name in U
From: Matteo Facchinetti
On platform mpc512x, PSC clock name registered by clk_register()
(clock.c:703) has _mclk suffix.
In mpc512x uart device driver, PSC clock name has _clk suffix.
So change PSC clock name in UART device driver using registered clock.
Signed-off-by: Matteo Facchinetti
---
On 03/12/2013 02:40:39 AM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, March 09, 2013 8:49 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/85
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> Some minor changes to the common corenet_ds.c code are needed to support
> the T4240QDS:
> * Add support for "fsl,qoriq-pcie-v3.0" controller
> * Bump max # of IRQs to 512 (T4240 supports more interrupts than
> previous SoCs).
>
> Signed-off-by: K
On Mar 5, 2013, at 5:16 PM, Kumar Gala wrote:
> * Add support for up to 24 cores on T4240 (includes threads)
> * Enable AltiVec support (on T4240)
> * Add T4240QDS board into build
> * Other changes are due to general kernel update of defconfig
>
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> Signed-off-by: Minghuan Lian
> Signed-off-by: Roy Zang
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Andy Fleming
> Signed-off-by: Shaohui Xie
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Scott Wood
> Signed-off-by: Kumar Gala
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Roy ZANG
>
> The T4240 utilizes a new PCIe controller block that has some minor
> programming model differences from previous versions.
>
> The major one that impacts initialization is how we determine the link
> state. On the 3.x controll
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
> the Power Book-E Architecture. However there are some minor differences
> between it and other Book-E implementations.
>
> Add support to parse SPRN_TLB1PS for the variable
On Mar 7, 2013, at 1:58 PM, Kumar Gala wrote:
> Enable a baseline T4240 SoC to boot. There are several things missing
> from the device trees for T4240:
>
> * Proper PAMU topology information
> * DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
> * Prefetch Manager
> * Thermal monitor unit
> *
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Vakul Garg
>
> Add device tree for SEC (crypto engine) version 5.0 used on T4240.
>
> Signed-off-by: Vakul Garg
> Signed-off-by: Andy Fleming
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 ++
On Feb 28, 2013, at 2:46 AM, Ramneek Mehresh wrote:
> Add first usb controller node for qonverge qoriq platforms like
> B4860, etc
>
> Signed-off-by: Ramneek Mehresh
> ---
> Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> (branch next)
>
> arch/powerpc/boot/dts/fsl
On Mar 12, 2013, at 1:43 AM,
wrote:
> From: Tang Yuantian
>
> Config FSL_SOC does not depend on PPC_CLOCK anymore since the following
> commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
> Config CPM does not use PPC_CLOCK either currently. So remove them.
>
> PPC_CLOCK also
On Mar 12, 2013, at 3:03 PM, Scott Wood wrote:
> This is a commonly used ethernet card, especially with mainline kernels
> which lack datapath support.o
>
> Other changes are due to running savedefconfig.
>
> Signed-off-by: Scott Wood
> ---
>
> arch/powerpc/configs/corenet64_smp_defconfig |
On Feb 25, 2013, at 8:33 PM, Jiucheng Xu wrote:
> Due to the partition of JFFS2 overlaps with QE ucode firmware, So JFFS2
> will break QE ucode. Shrink JFFS2's partition to reserve the space of
> QE ucode firmware.
>
> Signed-off-by: Jiucheng Xu
> ---
> arch/powerpc/boot/dts/p1021rdb-pc.dtsi |
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder
>
> -also define a binding for fsl,eref-* properties
>
> Signed-off-by: Stuart Yoder
> ---
>
> -v3
> -converted EREF specific properties to fsl,eref-*
>
> .../devicetree/bindings/powerpc/fsl/cpus.txt | 21 +++
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder
>
> Signed-off-by: Stuart Yoder
> ---
>
> -v2
> -deo is EREF specific, changed name of property
>
> arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 +
> arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 +
> 2 f
On Mar 12, 2013, at 3:44 PM, Kumar Gala wrote:
>
> On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
>
>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>>
>>> Rather than do it this way, we should do something like:
>>>
>>> fsl_indirect_read_config() {
>>> link check
>>> if (
On Mar 10, 2013, at 9:36 PM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Saturday, March 09, 2013 4:38 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
>> Subject:
On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>
>> Rather than do it this way, we should do something like:
>>
>> fsl_indirect_read_config() {
>> link check
>> if (link)
>> indirect_read_config()
>> }
>>
>> and
Hi Aneesh,
On Tue, 2013-03-12 at 12:49 +0530, Aneesh Kumar K.V wrote:
> Done. I added this as a patch on top of the series.
I tried to test this against v3.8, but applying it failed:
Applying: powerpc: Update kernel VSID range
error: patch failed: arch/powerpc/mm/slb_low.S:66
Could you pleas
This is a commonly used ethernet card, especially with mainline kernels
which lack datapath support.o
Other changes are due to running savedefconfig.
Signed-off-by: Scott Wood
---
arch/powerpc/configs/corenet64_smp_defconfig |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff
On Tuesday 12 March 2013 19:03:39 Chen Yuanquan-B41889 wrote:
> On 03/12/2013 06:30 PM, Rojhalat Ibrahim wrote:
> > On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=freescale..
From: "Aneesh Kumar K.V"
Now we use ESID_BITS of kernel address to build proto vsid. So rename
USER_ESIT_BITS to ESID_BITS
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 16
arch/powerpc/kernel/exceptions-64s.S |2 +-
arch/powerpc/kvm/book3s
From: "Aneesh Kumar K.V"
This patch change the kernel VSID range so that we limit VSID_BITS to 37.
This enables us to support 64TB with 65 bit VA (37+28). Without this patch
we have boot hangs on platforms that only support 65 bit VA.
With this patch we now have proto vsid generated as below:
W
From: "Aneesh Kumar K.V"
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/pow
Commit 5ac47f7a6efb (powerpc: Relocate prom_init.c on 64bit) made
prom_init.c position independent by manually relocating its entries
in the TOC.
We get the address of the TOC entries with the __prom_init_toc_start
linker symbol. If __prom_init_toc_start ends up as an entry in the
TOC then we nee
On 03/12/2013 06:30 PM, Rojhalat Ibrahim wrote:
On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
fei.zang=freescale@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
Sent: Tuesday, March 12, 2013 5:23
On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
> >> -Original Message-
> >> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> >> fei.zang=freescale@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
> >> Sent: Tuesday, March 12, 2013 5:23 PM
> >> To: Kumar Gala
> >> Cc:
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
fei.zang=freescale@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
Sent: Tuesday, March 12, 2013 5:23 PM
To: Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] Make PCIe hotplug work with Freescale
> Is that OK if I use the following code?
...
> if (is_in_pci_mem_space(addr)) {
> if (!user_mode(regs)) {
> ret = probe_kernel_address(regs->nip, inst);
>
> if (!ret) {
> rd = get_rt(inst);
>
On Tue, Mar 05, 2013 at 09:48:26PM -0800, Sukadev Bhattiprolu wrote:
> Michael Ellerman [mich...@ellerman.id.au] wrote:
> | I suspect Arnaldo was either waiting for an ACK from Ben, or was
> | expecting Ben to take it?
>
> Arnaldo, here is an updated patch. If it is acked by Paul Mackerras,
> Mich
On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>
> Rather than do it this way, we should do something like:
>
> fsl_indirect_read_config() {
> link check
> if (link)
> indirect_read_config()
> }
>
> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>
> - k
>
The MPIC chip with version 2.0 has a MSI errata (errata PIC1 of mpc8544),
It causes that neither MSI nor MSI-X can work fine. This is a workaround
to allow MSI-X to function properly.
Signed-off-by: Liu Shuo
Signed-off-by: Li Yang
Signed-off-by: Jia Hongtao
---
arch/powerpc/sysdev/fsl_msi.c |
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, March 09, 2013 8:49 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
> PCIe erratum on
From: Tang Yuantian
This adds the clock driver support for Freescale E500MC, E5500,
E6500 series SoCs using common clock framework.
Signed-off-by: Tang Yuantian
---
arch/powerpc/platforms/Kconfig.cputype |1 +
drivers/clk/Kconfig|7 +
drivers/clk/Makefile
From: Tang Yuantian
Signed-off-by: Tang Yuantian
---
take p5020 for example.
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 44 ++-
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi |2 +
2 files changed, 45 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/d
David Gibson writes:
> On Fri, Feb 15, 2013 at 09:09:38PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
snip
>> - * - We allow for USER_ESID_BITS significant bits of ESID and
>> - * CONTEXT_BITS bits of context for user addresses.
>> - * i.e. 64T (46 bits) of addre
From: Tang Yuantian
Config FSL_SOC does not depend on PPC_CLOCK anymore since the following
commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
Config CPM does not use PPC_CLOCK either currently. So remove them.
PPC_CLOCK also keeps Freescale PowerPC archtecture from supporting CO
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