On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote: > From: Roy ZANG <tie-fei.z...@freescale.com> > > The T4240 utilizes a new PCIe controller block that has some minor > programming model differences from previous versions. > > The major one that impacts initialization is how we determine the link > state. On the 3.x controllers we have a memory mapped SoC register > instead of a PCI config register that reports the link state. > > Signed-off-by: Roy Zang <tie-fei.z...@freescale.com> > Signed-off-by: Andy Fleming <aflem...@freescale.com> > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> > --- > arch/powerpc/sysdev/fsl_pci.c | 29 ++++++++++++++++++++++++++--- > arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++ > 2 files changed, 37 insertions(+), 3 deletions(-)
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