Hello Pankaj, Rajan
DO you have any comments on the below patch of gianfar?
> > - fsl,num_rx_queues = <0x8>;
> > - fsl,num_tx_queues = <0x8>;
Have been removed from P1010RDB device tree to avoid a kernel panic.
Kumar, as such I see this is the old dts format. A
Thanks Kumar for reviewing this patch.
Please find my response in-lined..
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Saturday, March 17, 2012 1:43 AM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; devicetree-disc...@lists.ozlabs
On Fri, 2012-03-16 at 17:48 -0600, Bjorn Helgaas wrote:
> We believe there's no reason to prevent reallocation on PA Semi, so
> revert to the default of "allow reallocation if necessary."
>
Acked-by: Benjamin Herrenschmidt
> CC: linuxppc-dev@lists.ozlabs.org
> Tested-by: Olof Johansson
> Acked-
On Fri, 2012-03-16 at 17:48 -0600, Bjorn Helgaas wrote:
> Normal PCI enumeration via PCI config space uses __pci_read_base(), where
> the PCI core applies any bus-to-resource offset. But powerpc doesn't use
> that path when enumerating via the device tree.
>
> In 6c5705fec63d, I converted powerpc
We believe there's no reason to prevent reallocation on PA Semi, so
revert to the default of "allow reallocation if necessary."
CC: Benjamin Herrenschmidt
CC: linuxppc-dev@lists.ozlabs.org
Tested-by: Olof Johansson
Acked-by: Olof Johansson
Signed-off-by: Bjorn Helgaas
---
arch/powerpc/platfor
Normal PCI enumeration via PCI config space uses __pci_read_base(), where
the PCI core applies any bus-to-resource offset. But powerpc doesn't use
that path when enumerating via the device tree.
In 6c5705fec63d, I converted powerpc to use the PCI core bus-to-resource
conversion, but I missed thes
The following changes since commit aba0eb84c87928992c021d33ef3ea59c931086b9:
Merge branch 'eeh' into next (2012-03-13 10:15:35 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Claudiu Manoil (2):
powerpc/85xx: Fix comp
On Fri, 2012-03-16 at 16:21 -0500, Kumar Gala wrote:
> Guys,
>
> Are you aware of any reason that we can't call of_platform_bus_probe()
> or multiple times. Timur's run into an issue in which all devices
> don't get registered properly if we call of_platform_bus_probe() times
> with different of_
Guys,
Are you aware of any reason that we can't call of_platform_bus_probe() or
multiple times. Timur's run into an issue in which all devices don't get
registered properly if we call of_platform_bus_probe() times with different
of_device_id struct's.
- k
_
Guys,
I'm not sure what the state of the EDAC patches and latest kernel are.. I'm
going to mark the ones in patch works as 'dead' and hopefully you guys will
resend if there is still an interest.
- k
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On Feb 10, 2012, at 2:09 AM,
wrote:
> From: Liu Shuo
>
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-
On Mar 16, 2012, at 3:42 PM, Scott Wood wrote:
> On 03/16/2012 03:35 PM, Kumar Gala wrote:
>> On Feb 10, 2012, at 2:09 AM,
>> wrote:
>>> +static int is_in_pci_mem_space(phys_addr_t addr)
>>> +{
>>> + struct pci_controller *hose;
>>> + struct resource *res;
>>> + int i;
>>> +
>>> + list
Kumar Gala wrote:
> This seems like paper taping over the real issue. We should be able to call
> of_platform_bus_probe() multiple times.
I tried debugging it, but I couldn't figure it out. My guess is that the
nodes probed by of_platform_bus_probe() are somehow "reserved", so that
the second
On Nov 30, 2011, at 10:19 AM, Timur Tabi wrote:
> Commit 46d026ac ("powerpc/85xx: consolidate of_platform_bus_probe calls")
> replaced platform-specific of_device_id tables with a single function
> that probes the most of the busses in 85xx device trees. If a specific
> platform needed additiona
On 03/16/2012 03:35 PM, Kumar Gala wrote:
> On Feb 10, 2012, at 2:09 AM,
> wrote:
>> +static int is_in_pci_mem_space(phys_addr_t addr)
>> +{
>> +struct pci_controller *hose;
>> +struct resource *res;
>> +int i;
>> +
>> +list_for_each_entry(hose, &hose_list, list_node) {
>> +
On Jan 8, 2012, at 11:45 PM,
wrote:
> From: Jerry Huang
>
> For all mpc85xx DS/MDS boards, we should check the return value from
> function "fsl_add_bridge", otherwise, when pcie node status is disabled,
> the kernel will panic when perform the function "pci_find_hose_for_OF_device"
> becaus
On Feb 10, 2012, at 2:09 AM,
wrote:
> From: Liu Shuo
>
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Create mpc8548cds_36b.dts. Support 36-bit mode.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 ++
> 1 files changed, 86 insertions(+), 0 deletions(-)
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> * Create mpc8548cds.dtsi.
> * Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
> * Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
> * Rename mpc8548cds.dts to mpc8548cds_32b.dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Correct ethernet1 and add ethernet2 and ethernet3.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi |4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
applied
- k
__
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Enable RapidIO and add rapidio and rmu nodes to dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16
> arch/powerpc/boot/dts/mpc8548
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts | 40 +-
> 1 files changed, 39 insertions(+), 1 deletions(-)
applied
- k
__
On Mar 14, 2012, at 5:15 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>
> The bootloader sets the PCI bridge to open a window from 0x
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> res
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts |8 -
> arch/powerpc/platforms/85xx/mpc85xx_cds.c |
>
>
> diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> new file mode 100644
> index 000..d274c014
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> @@ -0,0 +1,179 @@
> +/*
> + * BSC9131 RDB Device Tree Source stub (no addresses or t
On Feb 21, 2012, at 1:53 PM, Timur Tabi wrote:
> Remove the "select PHYS_64BIT" from the Kconfig entry for the P1022DS,
> so that large physical address support is a selectable option for non-CoreNet
> reference boards.
>
> The option is enabled in mpc85xx_[smp_]defconfig so that the default is
On Feb 21, 2012, at 11:44 PM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 77 -
> 1 files changed, 76 insertions(+), 1 deletions(-)
applied
- k
__
On Feb 21, 2012, at 11:44 PM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for
> qe, so
> they need to go in common header, the patch abstract them to fsl_guts.h
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/includ
On Feb 22, 2012, at 4:20 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
applied
- k
On Mar 6, 2012, at 11:20 PM, Shengzhou Liu wrote:
> From: Liu Shuo
>
> Fix the compatible string of sec 4.0 to match with CAMM driver according
> to Documentation/devicetree/bindings/crypto/fsl-sec4.txt
>
> Signed-off-by: Liu Shuo
> Signed-off-by: Shengzhou Liu
> ---
> v2: refine description
On 03/16/2012 02:32 PM, Kumar Gala wrote:
>
> On Feb 1, 2012, at 9:50 AM, Diana Craciun wrote:
>
>> From: Diana CRACIUN
>>
>> The MSIIR register for each MSI bank is aliased to a different
>> address. The MSI node reg property was updated to contain this
>> address:
>>
>> e.g. reg = <0x41600 0x2
On Feb 1, 2012, at 11:05 AM, Claudiu Manoil wrote:
> CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:209:13: error: 'THIS_MODULE' undeclared
> here (not in a function)
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:229:20: error: expected declaration
> specifiers
On Jan 31, 2012, at 4:15 AM, Claudiu Manoil wrote:
> fsl_85xx_l2ctlr.o and fsl_85xx_cache_sram.o are built only
> if CONFIG_FSL_85XX_CACHE_SRAM is defined. The driver that
> qualifies and wants to make use of the CACHE SRAM's exported
> API (i.e. a freescale net driver) should (be able to) select
On Feb 27, 2012, at 6:25 AM, Paul Gortmaker wrote:
> The mpc836x_mds platform has been broken since the commit
> 6fe3264945ee63292cdfb27b6e95bc52c603bb09
>
> "netdev/phy: Use mdiobus_read() so that proper locks are taken"
>
> which caused the fsl_pq_mdio TBI autoprobe to oops. The oops
> was
On Feb 9, 2012, at 7:41 AM, Diana Craciun wrote:
> From: Diana CRACIUN
>
> The association in the decice tree between PCI and MSI
> using fsl,msi property was an artificial one and it does
> not reflect the actual hardware.
>
> Signed-off-by: Diana CRACIUN
> ---
> arch/powerpc/boot/dts/p2041r
On Feb 1, 2012, at 9:50 AM, Diana Craciun wrote:
> From: Diana CRACIUN
>
> The MSIIR register for each MSI bank is aliased to a different
> address. The MSI node reg property was updated to contain this
> address:
>
> e.g. reg = <0x41600 0x200 0x44140 4>;
>
> The first region contains the add
On Dec 21, 2011, at 1:10 AM, Jia Hongtao wrote:
> Power supply for PCI inbound/outbound window registers is off when system
> go to deep-sleep state. We save the values of registers before suspend
> and restore to registers after resume.
>
> Signed-off-by: Jiang Yutang
> Signed-off-by: Jia Hong
Kumar Gala wrote:
> If you are doing this clean, just finish it. There are only a small handful
> of users of ccsr_guts_8{5,6}xx:
>
> arch/powerpc/include/asm/fsl_guts.h:static inline void guts_set_dmacr(struct
> ccsr_guts_86xx __iomem *guts,
> arch/powerpc/include/asm/fsl_guts.h:static inline
Kumar Gala wrote:
> Sticking with my original point of not applying this til PAMU driver is ready
> as well.
Ok.
--
Timur Tabi
Linux kernel developer at Freescale
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On Feb 16, 2012, at 11:21 AM, Timur Tabi wrote:
> Add a defintion of register PAMUBYPENR (offset 0x604) to the global
> utilities structure.
>
> PAMUBYPENR is the PAMU bypass enable register. It contains control
> bits for enabling bypass mode on each PAMU.
>
> Signed-off-by: Timur Tabi
> ---
On Feb 16, 2012, at 11:21 AM, Timur Tabi wrote:
> Remove the check for CONFIG_PPC_85xx and CONFIG_PPC_86xx from fsl_guts.h.
> The check was originally intended to allow the same header file to
> be used on 85xx and 86xx systems, even though the Global Utilities
> register could be different. It
On Feb 9, 2012, at 8:27 PM, Jia Hongtao-B38951 wrote:
> Hi Kumar,
> This series of patches have been pending for a long time.
> I'd like to know whether they are look good or not so I can do the further
> work on it.
> It's kind of emergency things for me.
> Thanks a lot for your attention.
I c
On 03/15/2012 08:30 PM, Poonam Aggrwal wrote:
> From: Poonam Aggrwal
>
> This TDM controller is available in various Freescale SOCs like MPC8315,
> P1020,
> P1022, P1010.
>
> Signed-off-by: Sandeep Singh
> Signed-off-by: Poonam Aggrwal
> ---
> Documentation/devicetree/bindings/tdm/fsl-tdm.t
On Nov 18, 2011, at 11:50 AM, Timur Tabi wrote:
> When the P1022's DIU video controller is active, the pixis must be accessed
> in "indirect" mode, which uses localbus chip select addresses.
>
> Switching between the DVI and LVDS monitor ports is handled by the pixis,
> so that switching needs t
On Mar 12, 2012, at 12:13 PM, Martyn Welch wrote:
> Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
> processor.
>
> Signed-off-by: Martyn Welch
> ---
>
> v2: Rebase patch onto powerpc/next, taking work by Kyle Moffett into
>account.
>
> v3: Correct detection of
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
> Move the GE PIC drivers to allow these to be used by non-86xx boards.
>
> Signed-off-by: Martyn Welch
> ---
>
> v2: Move GPIO and PIC drivers to sysdev/ge/ rather than platforms/.
>
> v3: Now just PIC driver. GPIO driver going to drivers/gpi
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
> The GE GPIO driver provides basic support (set direction, read/write state)
> for the GPIO provided on some GE single board computers. This patch moves
> the driver from the 86xx specific platform directrory to the GPIO subsystem
> so that it ca
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
> This patch adds the GE_FPGA configuration option. This is being carried
> out as ground work to allow the PIC and GPIO drivers to be move from the
> powerpc 86xx platform directory to more general locations to allow them to
> be used on non-86xx
Kumar Gala wrote:
>> > Haiying said it should be ok, but I haven't tried it yet. I'll try it on
>> > Monday.
> Did you ever test this?
No, I forgot all about it. I'll try it today, assuming the lone 8323
board in the board farm still works.
--
Timur Tabi
Linux kernel developer at Freescale
On Feb 10, 2012, at 12:48 AM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> P1020RDB-PC Overview
> --
> 1Gbyte DDR3 SDRAM
> 32 Mbyte NAND flash
> 10 16Mbyte NOR flash
> 16 Mbyte SPI flash
> SD connector to interface with the SD memory card
> Real-time clock on I2C bus
>
> PCIe:
On Feb 10, 2012, at 12:48 AM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 +++-
> 1 files changed, 23 insertions(+), 1 deletions(-)
applied
- k
___
On Mar 14, 2012, at 4:08 AM,
wrote:
> From: Jerry Huang
>
> The p1020mbg-pc has the similar feature as the p1020rdb.
> Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board.
> Overview of P1020MBG-PC platform:
>- DDR3 2GB
>- NOR flash 64MB
>- I2C EE
On Mar 14, 2012, at 4:08 AM,
wrote:
> From: Jerry Huang
>
> The p1020utm-pc has the similar feature as the p1020rdb.
> Therefore, p1020utm-pc use the same platform file as the p1/p2 rdb board.
> Overview of P1020UTM-PC platform:
>- DDR3 1GB
>- NOR flash 32MB
>- I2C EE
On Mar 15, 2012, at 12:34 AM, Prabhakar Kushwaha wrote:
> Integrated Flash Controller(IFC) can be used to hook NAND Flash
> chips using NAND Flash Machine available on it.
>
> Signed-off-by: Dipen Dudhat
> Signed-off-by: Scott Wood
> Signed-off-by: Li Yang
> Signed-off-by: Liu Shuo
> Signed-
On Mar 14, 2012, at 4:08 AM,
wrote:
> From: Jerry Huang
>
> The p1020mbg-pc has the similar feature as the p1020rdb.
> Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board.
> Overview of P1020MBG-PC platform:
>- DDR3 2GB
>- NOR flash 64MB
>- I2C EE
On Feb 20, 2012, at 8:11 PM, Jia Hongtao wrote:
> Signed-off-by: Jin Qing
> Signed-off-by: Jia Hongtao
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8572ds.dtsi | 50 +
> 1 files changed, 32 insertions(+), 18 deletions(-)
applied
- k
_
On Feb 15, 2012, at 6:25 PM, Timur Tabi wrote:
> The Freescale P1022 has a unique pin muxing "feature" where the DIU video
> controller's video signals are muxed with 24 of the local bus address signals.
> When the DIU is enabled, the bulk of the local bus is disabled, preventing
> access to memo
On Feb 15, 2012, at 6:25 PM, Timur Tabi wrote:
> Create a 32-bit address space version of p1022ds.dts. To avoid confusion,
> p1022ds.dts is renamed to p1022ds_36b.dts. We also create p1022ds.dtsi
> to store some common nodes.
>
> Signed-off-by: Timur Tabi
> ---
> arch/powerpc/boot/dts/p1022ds
On Jan 17, 2012, at 3:59 AM, Xie Xiaobo wrote:
> The properties indicates that the hardware supports waking up via magic
> packet.
>
> Signed-off-by: Xie Xiaobo
> ---
> arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi |3 ++-
> arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi |3 ++-
> arch/powerp
On Jan 17, 2012, at 3:59 AM, Xie Xiaobo wrote:
> 1. Add partitions for NOR and NAND Flash.
> 2. Additional attributes for sdhc.
>
> Signed-off-by: Xie Xiaobo
> ---
> arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi |5 ++
> arch/powerpc/boot/dts/mpc8536ds.dts |6 ++-
> arch/powerpc
On Mar 14, 2012, at 4:08 AM,
wrote:
> + partition@0 {
> + /* 128KB for DTB Image */
> + reg = <0x0 0x0002>;
> + label = "NOR (RO) DTB Image";
> + read-only;
> + };
> +
How many times ar
On Mar 15, 2012, at 12:40 PM, Sebastian Andrzej Siewior wrote:
> It is not at 0xffa0. According to current u-boot source the NAND
> controller is always at 0xff80 and it is either at CS0 or CS1
> depending on NAND or NAND+NOR mode. In 36bit mode it is shifted to
> 0xfff80 but it has a
On Fri, Mar 16, 2012 at 04:52:07PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the char-misc tree got a conflict in
> drivers/char/viotape.c between commit ba7a4822b48f ("powerpc: Remove some
> of the legacy iSeries specific device drivers") from the powerpc tree and
>
On Mar 8, 2012, at 4:47 PM, soniccat@gmail.com wrote:
> From: Liu Shuo
>
> Signed-off-by: Liu Shuo
> ---
> arch/powerpc/sysdev/fsl_msi.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
applied
- k
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On Nov 24, 2011, at 7:57 AM, Tabi Timur-B04825 wrote:
> On Nov 24, 2011, at 1:55 AM, Kumar Gala wrote:
>
>>>
>>> I'll have to check. But this patch can't be applied as-is unless it's
>>> proven safe for all QE-enabled chips.
>>
>> Any update on trying this on a MPC8323?
>
> Haiying said it
On Aug 11, 2011, at 9:25 AM, Robin Holt wrote:
> If I have the the fsl,num_rx_queues and fsl,num_tx_queues properties
> defined in the p1010's device tree file, I get a kernel panic very
> shortly after boot. The failure indicates we are configuring the
> gianfar.c driver for a queue depth great
On Jan 18, 2012, at 1:39 PM, Kumar Gala wrote:
> Add basic support for e6500 core in its single threaded mode.
>
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/include/asm/cputable.h | 12
> arch/powerpc/kernel/cputable.c | 18 ++
> 2 files changed, 26 inse
On Jan 18, 2012, at 1:39 PM, Kumar Gala wrote:
> The registers that describe size supported by TLB are different on MMU
> v2 as well as we support power of two page sizes. For now we continue
> to assume that FSL variable size array supports all page sizes up to the
> maximum one reported in TLB
On Fri, Mar 16, 2012 at 03:16:54PM +1100, Stephen Rothwell wrote:
> so remove the code that tests for it.
>
> Cc: Greg Kroah-Hartman
> Signed-off-by: Stephen Rothwell
> ---
> drivers/tty/hvc/hvc_vio.c |4
> 1 files changed, 0 insertions(+), 4 deletions(-)
>
> Greg, it is probably easi
On Mar 8, 2012, at 4:47 PM, soniccat@gmail.com wrote:
> From: Liu Shuo
>
> Signed-off-by: Liu Shuo
> ---
> arch/powerpc/sysdev/fsl_msi.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
applied
- k
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On Mar 15, 2012, at 12:40 PM, Sebastian Andrzej Siewior wrote:
> This is here most likely since the FSL bsp. Back in the FSL bsp it was
> set to 50Mhz and working. However the driver divided the SoC freq. only
> by 2. According to the TRM the platform clock (which the manual refers
> in its formu
On Feb 28, 2012, at 1:43 PM, Gustavo Zacarias wrote:
> Fix typo introduced by "powerpc: Add TBI PHY node to first MDIO bus"
> from Andy Fleming.
> It's device_type rather than device-type, which causes the mdio probe to
> fail thus making all gianfar ethernet interfaces unusable.
>
> Signed-off-
On Mar 9, 2012, at 2:10 AM, Liu Gang wrote:
> For the file "arch/powerpc/sysdev/fsl_rmu.c", there will be some compile
> errors while using the corenet64_smp_defconfig:
>
> .../fsl_rmu.c:315: error: cast from pointer to integer of different size
> .../fsl_rmu.c:320: error: cast to pointer from i
On Mar 5, 2012, at 8:58 PM, Liu Gang wrote:
> For the file "arch/powerpc/sysdev/fsl_rio.c", there will be some relocation
> errors while using the corenet64_smp_defconfig:
>
> WARNING: modpost: Found 6 section mismatch(es).
> To see full details build your kernel with:
> 'make CONFIG_DEBUG_SECTI
On Feb 16, 2012, at 3:06 PM, Tabi Timur-B04825 wrote:
> On Tue, Feb 14, 2012 at 2:06 AM, Zhicheng Fan wrote:
>> From: Zhicheng Fan
>>
>> P1025RDB Overview
>> --
>> 1Gbyte DDR3 SDRAM
>> 32 Mbyte NAND flash
>> 16Mbyte NOR flash
>> 16 Mbyte SPI flash
>> SD connector to interface w
On Feb 16, 2012, at 3:07 PM, Tabi Timur-B04825 wrote:
> On Tue, Feb 14, 2012 at 2:06 AM, Zhicheng Fan wrote:
>> From: Zhicheng Fan
>>
>> Signed-off-by: Zhicheng Fan
>> ---
>
> Acked-by: Timur Tabi
>
> --
applied
- k
___
Linuxppc-dev mailing li
On Jan 17, 2012, at 11:40 PM, Ramneek Mehresh wrote:
> Add usb controller version info for the following:
> MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041,
> P3041, P3060, P5020
>
> Signed-off-by: Ramneek Mehresh
> ---
> Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/p
On Feb 10, 2012, at 1:59 AM,
wrote:
> From: Tang Yuantian
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Tang Yuantian
> ---
> v3:
> -correct the patch author
>
> arch/powerpc/boot/dts/p2020rdb-pc.dtsi| 241 +
Hi Josh,
On Fri, 16 Mar 2012 09:41:38 -0400 Josh Boyer wrote:
>
> Stephen, could you change linux-next to pull from this tree instead of the
> infradead one?
Done.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
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Hi Ben,
A small pull request for linux-next. This adds some commits for Bluestone
from APM, and updates the location of my tree in MAINTAINERS back to
kernel.org.
Stephen, could you change linux-next to pull from this tree instead of the
infradead o
On Mon, Mar 12, 2012 at 4:07 AM, Mai La wrote:
> diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c
> b/arch/powerpc/sysdev/ppc4xx_msi.c
> index 1c2d7af..63989d0 100644
> --- a/arch/powerpc/sysdev/ppc4xx_msi.c
> +++ b/arch/powerpc/sysdev/ppc4xx_msi.c
> @@ -28,10 +28,11 @@
> #include
> #include
>
On Fri, 16 Mar 2012, Stephen Rothwell wrote:
> Today's linux-next merge of the trivial tree got a conflict in
> drivers/char/viotape.c between commit ba7a4822b48f ("powerpc: Remove some
> of the legacy iSeries specific device drivers") from the powerpc tree and
> commit a7ccf3775219 ("char: Fix ty
From: Li Yang
* Added compatible "fsl,p1022-pmc".
* Added clock nodes to control the clock of wake-up source.
* Used "fsl,pmc-handle" property to connect device and clock node.
Signed-off-by: Li Yang
Signed-off-by: Zhao Chenhui
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 65
Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
This patch adds the support to change CPU frequency using the standard
cpufreq interface. The ratio CORE to CCB can be 1:1(except MPC8536), 3:2,
2:1, 5:
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu
Signed-off-by: Li Yang
Signed-off-by: Jin Qing
Signed-off-by: Zhao Chenhui
---
arch/powerpc/sysdev/fsl_pmc.c | 71 ++
From: Li Yang
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
While in deep sleep PM mode, ad
From: Li Yang
Add support to disable and re-enable individual cores at runtime
on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core.
MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off.
This patch uses the boot page from bootloader to boot core at runtime.
It suppo
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