On Jan 18, 2012, at 1:39 PM, Kumar Gala wrote: > The registers that describe size supported by TLB are different on MMU > v2 as well as we support power of two page sizes. For now we continue > to assume that FSL variable size array supports all page sizes up to the > maximum one reported in TLB1PS. > > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> > --- > arch/powerpc/include/asm/reg_booke.h | 1 + > arch/powerpc/mm/fsl_booke_mmu.c | 19 +++++++++++++------ > 2 files changed, 14 insertions(+), 6 deletions(-)
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