On Mar 15, 2012, at 12:40 PM, Sebastian Andrzej Siewior wrote: > This is here most likely since the FSL bsp. Back in the FSL bsp it was > set to 50Mhz and working. However the driver divided the SoC freq. only > by 2. According to the TRM the platform clock (which the manual refers > in its formula) is the system clock divided by two. So in the end it has > to divide by 4 and this is what the fsl-spi driver in tree is doing. > Since then the flash is not wokring I guess. After chaning the freq from > 50Mhz to 40Mhz like others do then I can access the flash. > > Signed-off-by: Sebastian Andrzej Siewior <bige...@linutronix.de> > --- > arch/powerpc/boot/dts/p1010rdb.dtsi | 2 +- > arch/powerpc/boot/dts/p2020rdb.dts | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-)
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