The max possible value for DCTL.LPM_NYET_THRES is 15 and not 255. Change
the default value to 15.
Cc: sta...@vger.kernel.org
Fixes: 80caf7d21adc ("usb: dwc3: add lpm erratum support")
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 2 +-
1 file changed, 1 insertion(+),
The macro name DWC3_DCTL_LPM_ERRATA is uninformative and does not do
masking. Remove DWC3_DCTL_LPM_ERRATA_MASK and rename
DWC3_DCTL_LPM_ERRATA to DWC3_DCTL_NYET_THRES with proper masking.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 3 +--
drivers/usb/dwc3/gadget.c | 2 +-
2
DWC3 is missing the printing of control request GET_STATUS(device)
tracepoint. This patch prints that.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/debug.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
index 6759a7efd8d5
The setting of the dr_mode may need to check the controller's revision.
The revision is set in the dwc3_core_is_valid(), which comes after
dr_mode setting. Let's move it closer to the start of the dwc3_probe()
function and before calling dwc3_get_dr_mode().
Signed-off-by: Th
All DWC3 controllers are LPM capable. Report that in the
usb_gadget.lpm_capable for the gadget driver to properly output the
bcdUSB value in the descriptor.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/gadget.c b
Hi,
Anurag Kumar Vulisha wrote:
> Hi Thinh,
>
>> -Original Message-----
>> From: Thinh Nguyen [mailto:thinh.ngu...@synopsys.com]
>> Sent: Friday, May 10, 2019 5:30 AM
>> To: Anurag Kumar Vulisha ; Thinh Nguyen
>> ; Greg Kroah-Hartman
>> ; Rob Herring
patch disables the
hub-initated U1/U2 if the device-initiated U1/U2 entry fails.
Reference: USB 3.2 spec 7.2.4.2.3
Signed-off-by: Thinh Nguyen
---
drivers/usb/core/hub.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/core/hub.c b
SET_FEATURE(U1/U2_ENABLE) and CLEAR_FEATURE(U1/U2) only apply while the
device is in configured state. Add proper check in usb_disable_lpm() and
usb_enable_lpm() for enabling/disabling device-initiated U1/U2.
Signed-off-by: Thinh Nguyen
---
drivers/usb/core/hub.c | 4 ++--
1 file changed, 2
Hi Anurag,
Anurag Kumar Vulisha wrote:
> Hi Thinh,
>
>> -Original Message-----
>> From: Thinh Nguyen [mailto:thinh.ngu...@synopsys.com]
>> Sent: Saturday, May 11, 2019 7:18 AM
>> To: Anurag Kumar Vulisha ; Thinh Nguyen
>> ; Greg Kroah-Hartman
>> ; Ro
Hi Baruch,
Baruch Siach wrote:
> Hi Jun Li,
>
> On Wed, May 08, 2019 at 10:52:37AM +, Jun Li wrote:
>> From: Jun Li
>>
>> Register access in core validation may hang before the bulk
>> clks are enabled.
> This patch fixes the hang issue for on my i.MX8MQ based system.
>
> Tested-by: Baruch Si
Hi,
John Youn wrote:
>> -Original Message-
>> From: Felipe Balbi
>> Sent: Friday, June 7, 2019 2:50 AM
>> To: John Youn
>> Cc: linux-usb@vger.kernel.org
>> Subject: [RFC] Sorting out dwc3 ISOC endpoints once and for all
>>
> ++ Thinh
>
> Hi Felipe,
>
> Sorry, missed this e-mail.
>
>> Now
Felipe Balbi wrote:
> Hi,
>
> Thinh Nguyen writes:
>>>> static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct
>>>> dwc3_request *req)
>>>>
>>>>
>>>> Would there be any obvious draw-back to going down this route? The t
Thinh Nguyen wrote:
> Felipe Balbi wrote:
>> Hi,
>>
>> Thinh Nguyen writes:
>>>>> static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct
>>>>> dwc3_request *req)
>>>>>
>>>>>
>>>>> Would ther
Felipe Balbi wrote:
> Hi,
>
> Thinh Nguyen writes:
>>>>>> Would there be any obvious draw-back to going down this route? The thing
>>>>>> is that, as it is, it seems like we will *always* have some corner case
>>>>>> where we
Hi,
Thinh Nguyen wrote:
> Felipe Balbi wrote:
>> Hi,
>>
>> Thinh Nguyen writes:
>>>>>>> Would there be any obvious draw-back to going down this route? The thing
>>>>>>> is that, as it is, it seems like we will *always* have some corn
Hi,
claus.stovga...@gmail.com wrote:
> Hi
>
> I have earlier worked with the possibility for disabling U1/U2 to solve
> an issue where the dwc3 acting as a gadget device sometimes failing to
> leave U2.
>
> Analyzing the situation when the dwc3 failing to leave U2, it happens
> when the link is in
Hi,
John Stultz wrote:
> On Fri, Jun 28, 2019 at 3:58 PM Sasha Levin wrote:
>> On Fri, Jun 28, 2019 at 06:24:04PM +, John Stultz wrote:
>>> With recent changes in AOSP, adb is using asynchronous io, which
>>> causes the following crash usually on a reboot:
>>>
>>> [ 184.278302] BUG: scheduli
Hi,
Alan Stern wrote:
> On Fri, 10 May 2019, EJ Hsu wrote:
>
>> This change is to fix below warning message in following scenario:
>> usb_composite_setup_continue: Unexpected call
>>
>> When system tried to enter suspend, the fsg_disable() will be called to
>> disable fsg driver and send a signal
Thinh Nguyen wrote:
> Alan Stern wrote:
>> On Tue, 2 Jul 2019, Thinh Nguyen wrote:
>>
>>> Hi,
>>>
>>> Alan Stern wrote:
>>>> On Fri, 10 May 2019, EJ Hsu wrote:
>>>>
>>>>> This change is to fix below warning m
Hi,
claus.stovga...@gmail.com wrote:
> On man, 2019-07-01 at 20:48 +0000, Thinh Nguyen wrote:
>> Hi,
>>
>>
>>>
>>> reg = dwc3_readl(dwc->regs, DWC3_DCTL);
>>> if (reg & DWC3_DCTL_INITU2ENA)
>>> param = dwc->u2pel;
>&g
Hi,
fei.y...@intel.com wrote:
> From: Fei Yang
>
> If scatter-gather operation is allowed, a large USB request is split into
> multiple TRBs. These TRBs are chained up by setting DWC3_TRB_CTRL_CHN bit
> except the last one which has DWC3_TRB_CTRL_IOC bit set instead.
> Since only the last TRB has
Hi Sasha,
Sasha Levin wrote:
> From: EJ Hsu
>
> [ Upstream commit e70b3f5da00119e057b7faa557753fee7f786f17 ]
>
> This change is to fix below warning message in following scenario:
> usb_composite_setup_continue: Unexpected call
>
> When system tried to enter suspend, the fsg_disable() will be cal
Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit
will not be cleared until after all the internal clocks are synchronized
during soft-reset. This may take a little more than 50ms. Set the
polling rate at 20ms instead.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c
GUSB3PIPECTL.SUSPENDABLE and
GUSB2PHYCFG.SUSPHY before core initialization and only set them after
the device soft-reset is completed.
Reference: DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section
1.2.49 and 1.2.45
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 37
>From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 13 -
1 file changed, 12 insertions(+), 1 delet
B counter for ep0 IN" from series
- Separate "usb: dwc3: gadget: Set maxpacket size for ep0 IN" from series
- Use msleep() instead of mdelay() for SoftReset PHY sync delay
- Rename new USB31 macros from DWC3_USB31_* to DWC31_*
- Rename device properties and replace '_&#
burst size|
+---+--+---+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8c3f28f3eff8..ce9edcf17738
DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b
|
+---+--+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1ecdc062df58..8c3f28f3eff8 100644
--- a/drivers
|
+---+---+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 09243a680a0d..1ecdc062df58 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -255,6 +255,8 @@
#define
threshold count and max
burst size properties must be set to a valid non-zero value 1-16.
DWC_usb31 programming guide section 1.2.3 and 1.2.4.
Cc: John Youn
Reviewed-by: Rob Herring
Signed-off-by: Thinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc3.txt | 16
1 file
Dump LSP and BMU debug info.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h| 5 +
drivers/usb/dwc3/debugfs.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 28d6f6511f6f..4f3b43809917 100644
--- a/drivers/usb
DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3
DWC_usb3 speed can only be set up to SuperSpeed. Limit the setting to
SuperSpeed only should the value be higher. Otherwise, the controller
will read an invalid speed value and set the device to an incorrect
speed.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 5 -
1 file
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new fields to store these threshold configurations.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 55 +
drivers/usb/dwc3/core.h | 8 +++
2 files changed
The maximum bytes per interval for USB SuperSpeed Plus can be set by
isoc endpoint companion descriptor when it is above 48K. If the
descriptor is provided, then use its value.
USB 3.1 spec 9.6.8
Acked-by: Felipe Balbi
Signed-off-by: Thinh Nguyen
---
Changes in v5:
- Separate from patch
Platform device is allocated before adding resources. Make sure to
properly cleanup on error case.
Fixes: f1c7e7108109 ("usb: dwc3: convert to pcim_enable_device()")
Signed-off-by: Thinh Nguyen
---
Changes in v2:
- Separate from patch series "usb: dwc3: pci: Make device propertie
Platform device is allocated before adding resources. Make sure to
properly cleanup on error case.
Cc:
Fixes: f1c7e7108109 ("usb: dwc3: convert to pcim_enable_device()")
Signed-off-by: Thinh Nguyen
---
Changes in v3:
- Include Cc:
Changes in v2:
- Separate from patch series "
Hi Felipe,
On 4/9/2018 4:28 AM, Felipe Balbi wrote:
> In case we get an event with status set to Missed Isoc, this means we
> have missed an isochronous interval and should issue End Transfer
> command and wait for the following XferNotReady.
Why does DWC3 need to issue End Transfer if there are
Hi,
On 4/10/2018 12:36 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> Hi Felipe,
>>
>> On 4/9/2018 4:28 AM, Felipe Balbi wrote:
>>> In case we get an event with status set to Missed Isoc, this means we
>>> have missed an is
Hi,
On 4/11/2018 1:21 AM, Felipe Balbi wrote:
>
> Hi,
>
> Felipe Balbi writes:
Without XferNotReady, we won't have a reliable way to know the uFrame
number. Read the Isochronous programming sequence from your databook.
>>>
>>> Right. We need XferNotReady to know when to start isoc tra
Hi,
On 4/12/2018 12:18 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> Hi,
>>
>> On 4/11/2018 1:21 AM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> Felipe Balbi writes:
>>>>>> Without XferNotReady,
Hi,
On 5/30/2018 11:49 PM, Felipe Balbi wrote:
> Paul Zimmerman writes:
>
>> Hi Felipe,
>>
>> Felipe Balbi writes:
>>
>> < snip >
>>
>>> thinking about this a little more. This extra list_empty() check is
>>> not wrong at all :-) I've amended this series with the 3 patches
>>> below. I'll resend
This driver is to be used for Synopsys PCIe-base HAPS platform. Move the
the HAPS support from dwc3-pci to this driver.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/Kconfig | 13 ++--
drivers/usb/dwc3/Makefile| 1 +
drivers/usb/dwc3/dwc3-haps.c | 137
Hi,
On 9/11/2017 12:42 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>>> Felipe Balbi writes:
>>>> Thinh Nguyen writes:
>>>>
>>>>> Hi Felipe,
>>>>>
>>>>> On 9/7/2017 12:16 AM, Felipe Balbi
DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b
DWC_usb31 periodic transfer at 48K+ bytes per interval may need
modification to the TX/RX packet threshold to achieve optimal result.
Add properties to make it configurable.
Cc: John Youn
Signed-off-by: Thinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++
1 file changed
|
+---+--+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 6ebf7ddc547d..7c4ba7f74f27 100644
--- a/drivers
burst size|
+---+--+---+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7c4ba7f74f27..ce10954afe49
>From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
cleared, we must wait at least 50ms before accessing the PHY domain
(synchronization delay).
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
d
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new variables to store these threshold configurations.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 57 +
drivers/usb/dwc3/core.h | 12 +++
2 files
|
+---+---+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4a4a4c98508c..6ebf7ddc547d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -239,6 +239,8 @@
#define
only. Check for the data direction and properly reset the
TRB counter from correct control endpoint.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/ep0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index fd3e7ad2eb0e
This patch series adds new updates and some fixes for DWC_usb31.
Thinh Nguyen (15):
usb: dwc3: Device SoftReset PHY synchonization delay
usb: core: urb: Check SSP isoc ep comp descriptor
usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields
usb: dwc3: Check IP revision for GTXFIFOSIZ
usb
The maximum bytes per interval for USB SuperSpeed Plus can be set by
isoc endpoint companion descriptor when it is above 48K. If the
descriptor is provided, then use its value.
USB 3.1 spec 9.6.8
Signed-off-by: Thinh Nguyen
---
drivers/usb/core/urb.c | 8
1 file changed, 8 insertions
microframe number for isochronous IN
endpoints.
Cc: John Youn
Signed-off-by: Thinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index
Dump LSP and BMU debug info.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h| 5 +
drivers/usb/dwc3/debugfs.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 83a74d10fa82..21a6dcd379f1 100644
--- a/drivers/usb
DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3
test1 fails, BIT[15:14] is 'b11
if test0 fails and test1 fails, BIT[15:14] is 'b10
if test0 fails and test1 passes, BIT[15:14] is 'b01
Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
endpoints.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 2 +
Add a new variable to dwc3 structure to track VERSIONTYPE. The
VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register.
In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE
such as "ea01" and "ea02".
Signed-off-by: Thinh Nguyen
---
drivers
driver will incorrectly calculate the data
transfer size and fail to send ZLP for HS/FS 3-stage control read
transfer.
The fix is simply to update the max packet size for the ep0 IN direction
during ConnectDone event.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 2 ++
1 file
On 1/5/2018 1:43 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 1/5/2018 11:16 PM, Thinh Nguyen wrote:
>
>> Add a new variable to dwc3 structure to track VERSIONTYPE. The
>
> That's called field, not variable.
Thanks for pointing that out. I'll make an upda
Hi,
On 1/8/2018 4:06 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> There are 2 control endpoint structures for DWC3. However, the driver
>> only updates the OUT direction control endpoint structure during
>> ConnectDone event. DWC3 driver needs to
On 1/8/2018 4:01 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
>> cleared, we must wait at least 50ms before accessing the PHY domain
>> (synchronization delay).
>
On 1/8/2018 4:02 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
>> is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.
>>
>> The GTXFIFOSIZ
Hi,
On 1/8/2018 4:08 AM, Felipe Balbi wrote:
> Thinh Nguyen writes:
>> Dump LSP and BMU debug info.
>>
>> Signed-off-by: Thinh Nguyen
>> ---
>> drivers/usb/dwc3/core.h| 5 +
>> drivers/usb/dwc3/debugfs.c | 5 +
>> 2 files changed, 10
Hi,
On 1/8/2018 4:05 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
>> with new variables to store these threshold configurations.
>
> couldn't we calculate these in runtim
Hi,
On 1/8/2018 8:12 PM, Rob Herring wrote:
> On Fri, Jan 05, 2018 at 12:14:48PM -0800, Thinh Nguyen wrote:
>> DWC_usb31 periodic transfer at 48K+ bytes per interval may need
>> modification to the TX/RX packet threshold to achieve optimal result.
>> Add properties to make it
This patch series fixes an issue with HS/FS 3-stage control read transfer where
DWC3 incorrectly check when to send ZLP.
Changes in v2:
- Separate from "usb: dwc3: Add new updates for DWC_usb31" patch series
- Add 'Cc' to stable mailing list
Thinh Nguyen (2):
us
driver will incorrectly calculate the data
transfer size and fail to send ZLP for HS/FS 3-stage control read
transfer.
The fix is simply to update the max packet size for the ep0 IN direction
during ConnectDone event.
Cc: sta...@vger.kernel.org
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3
only. Check for the data direction and properly reset the
TRB counter from correct control endpoint.
Cc: sta...@vger.kernel.org
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/ep0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb
IN" from series
- Use msleep() instead of mdelay() for SoftReset PHY sync delay
- Rename new USB31 macros from DWC3_USB31_* to DWC31_*
- Rename device properties and replace '_' with '-'
- Minor fixes in the commit messages
Thinh Nguyen (14):
usb: dwc3: Add SoftRe
>From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
cleared, we must wait at least 50ms before accessing the PHY domain
(synchronization delay).
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
d
|
+---+---+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4a4a4c98508c..70666d336e86 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -239,6 +239,8 @@
#define
|
+---+--+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 70666d336e86..61c2b78d5809 100644
--- a/drivers
The maximum bytes per interval for USB SuperSpeed Plus can be set by
isoc endpoint companion descriptor when it is above 48K. If the
descriptor is provided, then use its value.
USB 3.1 spec 9.6.8
Signed-off-by: Thinh Nguyen
---
drivers/usb/core/urb.c | 8
1 file changed, 8 insertions
DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b
DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3
burst size|
+---+--+---+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 61c2b78d5809..7d15d92f622a
DWC_usb31 periodic transfer at 48K+ bytes per interval may need
modification to the TX/RX packet threshold to achieve optimal result.
Add properties to make it configurable.
Cc: John Youn
Signed-off-by: Thinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc3.txt | 4
1 file changed, 4
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new fields to store these threshold configurations.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 55 +
drivers/usb/dwc3/core.h | 8 +++
2 files changed
Add a new field to dwc3 structure to track VERSIONTYPE. The VERSIONTYPE
is represented in ASCII in the 32-bit VERSIONTYPE register. In
DWC_usb31, sub releases for each version are tracked with VERSIONTYPE
such as "ea01" and "ea02".
Signed-off-by: Thinh Nguyen
---
drivers
microframe number for isochronous IN
endpoints.
Cc: John Youn
Signed-off-by: Thinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index
Dump LSP and BMU debug info.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h| 5 +
drivers/usb/dwc3/debugfs.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e53ae6038bbe..fd794972802d 100644
--- a/drivers/usb
: Thinh Nguyen
---
drivers/usb/gadget/legacy/mass_storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/legacy/mass_storage.c
b/drivers/usb/gadget/legacy/mass_storage.c
index ef3d25259b0e..fd5595ac5bf7 100644
--- a/drivers/usb/gadget/legacy/mass_storage.c
test1 fails, BIT[15:14] is 'b11
if test0 fails and test1 fails, BIT[15:14] is 'b10
if test0 fails and test1 passes, BIT[15:14] is 'b01
Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
endpoints.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 2 +
Hi,
On 1/11/2018 12:16 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> There are 2 control endpoint structures for DWC3. However, the driver
>> only updates the OUT direction control endpoint structure during
>> ConnectDone event. DWC3 driver needs to
Hi,
On 1/11/2018 12:16 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen writes:
>> In control read transfer completion handler, the driver needs to reset
>> the TRB enqueue counter. Since there is one control endpoint structure
>> for each direction, we must also
1" patch series
- Add 'Cc' to stable mailing list
Thinh Nguyen (2):
usb: dwc3: gadget: Set maxpacket size for ep0 IN
usb: dwc3: ep0: Reset TRB counter for ep0 IN
drivers/usb/dwc3/ep0.c| 7 ++-
drivers/usb/dwc3/gadget.c | 2 ++
2 files changed, 8 insertions(+), 1
the TRB counter from correct control endpoint.
Cc: sta...@vger.kernel.org
Fixes: c2da2ff00606 ("usb: dwc3: ep0: don't use ep0in for transfers")
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/ep0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers
USB3 DRD Driver")
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 639dd1b163a0..21abea0ac622 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
#x27;-'
- Minor fixes in the commit messages
Thinh Nguyen (15):
usb: dwc3: Add SoftReset PHY synchonization delay
usb: core: urb: Check SSP isoc ep comp descriptor
usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields
usb: dwc3: Check IP revision for GTXFIFOSIZ
usb: dwc3: Add DWC_usb31
>From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
cleared, we must wait at least 50ms before accessing the PHY domain
(synchronization delay).
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
d
The maximum bytes per interval for USB SuperSpeed Plus can be set by
isoc endpoint companion descriptor when it is above 48K. If the
descriptor is provided, then use its value.
USB 3.1 spec 9.6.8
Signed-off-by: Thinh Nguyen
---
drivers/usb/core/urb.c | 8
1 file changed, 8 insertions
|
+---+---+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4a4a4c98508c..70666d336e86 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -239,6 +239,8 @@
#define
DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b
|
+---+--+--+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 70666d336e86..61c2b78d5809 100644
--- a/drivers
DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/gadget.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3
burst size|
+---+--+---+
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 61c2b78d5809..7d15d92f622a
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new fields to store these threshold configurations.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.c | 55 +
drivers/usb/dwc3/core.h | 8 +++
2 files changed
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