t: dma0chan2-copy0: summary 10929638 tests, 0 failures
33984.39 iops 543750 KB/s (0)
[ 7757.003008] dmatest: dma0chan3-copy0: summary 11204208 tests, 0 failures
35759.65 iops 572154 KB/s (0)
Green Wan (3):
dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA
riscv: dts: add support for PDM
Add DT bindings document for Platform DMA(PDMA) driver of board,
HiFive Unleashed Rev A00.
Signed-off-by: Green Wan
---
.../bindings/dma/sifive,fu540-c000-pdma.yaml | 55 +++
MAINTAINERS | 5 ++
2 files changed, 60 insertions(+)
create mode
Add PDMA support to (arch/riscv/boot/dts/sifive/fu540-c000.dtsi)
Signed-off-by: Green Wan
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index
--
||--< done 27 >--|ch 2|
||--< err 28 >--|| (dma0chan2)
|| --
|| --
||--< done 29 >--|ch 3|
||--< err 30 >--| | (dma0chan3)
-- --
Signed-off-by: G
d fix separately.
Signed-off-by: Evan Green
---
Changes in v2:
- Enable and disable unconditionally (Dmitry)
drivers/input/touchscreen/atmel_mxt_ts.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c
b/drivers/input/touchscreen/atmel_mxt_ts.c
pending, but the interrupt is serviced before both the driver and
the underlying I2C bus have been resumed. This causes EREMOTEIO errors.
Disable the IRQ in suspend, and re-enable it if it was previously enabled
in resume.
Signed-off-by: Evan Green
---
drivers/input/touchscreen/atmel_mxt_ts.c
; On 7/11/2019 10:06 AM, Evan Green wrote:
> > Hi Georgi and David,
> >
> > On Tue, Jun 18, 2019 at 2:17 AM Georgi Djakov
> > wrote:
> >> From: David Dai
> >>
> >> Add support for wake and sleep commands by using a tag to indicate
> >> wh
On Mon, Apr 27, 2020 at 6:11 PM Dmitry Torokhov
wrote:
>
> On Mon, Apr 27, 2020 at 02:55:48PM -0700, Evan Green wrote:
> > Fix a use-after-free noticed by running with KASAN enabled. If
> > rmi_irq_fn() is run twice in a row, then rmi_f11_attention() (among
> > others)
an2-copy0: summary 45975 tests, 0 failures
41178.48 iops 328740 KB/s (0)
[ 267.590542] dmatest: dma0chan3-copy0: summary 44768 tests, 0 failures
38560.29 iops 307726 KB/s (0)
Green Wan (4):
dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA
riscv: dts: add support for PDMA device of Hi
Add DT bindings document for Platform DMA(PDMA) driver of board,
HiFive Unleashed Rev A00.
Reviewed-by: Rob Herring
Reviewed-by: Pragnesh Patel
Signed-off-by: Green Wan
---
.../bindings/dma/sifive,fu540-c000-pdma.yaml | 55 +++
1 file changed, 55 insertions(+)
create mode
Add PDMA support to (arch/riscv/boot/dts/sifive/fu540-c000.dtsi)
Signed-off-by: Green Wan
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index
Update MAINTAINERS for SiFive PDMA driver.
Signed-off-by: Green Wan
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a69e6db80c79..62d5b249be65 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14778,6 +14778,12 @@ F: drivers/media/usb
;--|ch 2|
||--< err 28 >--|| (dma0chan2)
|| --
|| --
||--< done 29 >--|ch 3|
||--< err 30 >--|| (dma0chan3)
-- --
Reviewed-by: Vinod Koul
Signed-off-by: Green Wan
Reported-by:
from memory-region
> arm64: dts: qcom: sc7180: Update reserved memory map
> arm64: dts: qcom: sc7180: Add Q6V5 MSS node
> arm64: dts: qcom: sc7180: Update Q6V5 MSS node
Tested-by: Evan Green
ies in my inbox.
Tested-by: Evan Green
got a tree that's running the
modem well.
Tested-by: Evan Green
On Thu, Mar 5, 2020 at 8:28 PM Alex Elder wrote:
>
> This series presents the driver for the Qualcomm IP Accelerator (IPA).
>
> This is version 2 of this updated series. It includes the following
> small changes since the previous version:
> - Now based on net-next instead of v5.6-rc
> - Conf
On Wed, Feb 13, 2019 at 6:40 PM Martin K. Petersen
wrote:
>
>
> Evan,
>
> > If the backing device for a loop device is a block device, then mirror
> > the discard properties of the underlying block device into the loop
> > device. While in there, differentiate between REQ_OP_DISCARD and
> > REQ_OP
Greetings, block experts!
I'm trying to track down a KASAN warning I'm seeing in our downstream
4.19 kernel, and I could use a little help. The warning looks like
this:
[ 224.564894] BUG: KASAN: use-after-free in bt_for_each+0x1ac/0x28c
[ 224.571195] Read of size 8 at addr ffc17c621340 by t
On Thu, Feb 14, 2019 at 11:33 AM Bart Van Assche wrote:
>
> On Thu, 2019-02-14 at 10:04 -0800, Evan Green wrote:
> > Greetings, block experts!
> >
> > I'm trying to track down a KASAN warning I'm seeing in our downstream
> > 4.19 kernel, and I could u
atch delete the complex MACRO and use a common if-else
> instead.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
uot;gals" clock for smi-larb.
>
> From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
> Control Unit) is connected with smi-common directly, we can take them
> as "larb2", "larb3" and "larb7", and their register spaces are
> different with the normal larb.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> range) register while mt2712 have. Move it into the plat_data.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
_data, it's also a preparing
> patch for mt8183.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Nicolas Boichat
Reviewed-by: Evan Green
>
> And, the base of smi-common is completely different with smi_ao_base
> of gen1, thus I add new variable for that.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
83 need reset_axi like mt8173.
> 7) the larb-id in smi-common is remapped. M4U should add its larbid_remap.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
Reviewed-by: Robin Murphy
> ---
> Comparing the previous version, I add MTK_4GB quirk always since mtk_iommu
> has already controlled the PA itself. Helped from Evan.
Thanks for all the explanation on this one. I think I understand it
now, and it looks good to me.
Reviewed-by: Evan Green
t;struct mtk_smi_iommu" could also
> be deleted.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Thanks for the cleanup.
Reviewed-by: Evan Green
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> This patch only rename the variable name from enable_4GB to
> dram_is_4gb for readable.
>
> Signed-off-by: Yong Wu
Nice, this is clearer.
Reviewed-by: Evan Green
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> In the 4GB mode, the physical address is remapped,
>
> Here is the detailed remap relationship.
> CPU PA ->HW PA
> 0x4000_ 0x1_4000_ (Add bit32)
> 0x8000_ 0x1_8000_ ...
> 0xc000_ 0x1_c000_
avoiding this error in the logs.
I can also confirm that this fixes test block/003 in the blktests, when
running blktests on a loop device backed by a block device.
Changes in v2:
- Unnested error if statement (Bart)
Evan Green (2):
loop: Report EOPNOTSUPP properly
loop: Better discard
been lumping together.
This change fixes blktest block/003, and removes an extraneous
error print in block/013 when testing on a loop device backed
by a block device that does not support discard.
Signed-off-by: Evan Green
---
Changes in v2: None
drivers/block/loop.c | 61
.
Signed-off-by: Evan Green
Reviewed-by: Ming Lei
---
Changes in v2:
- Unnested error if statement (Bart)
Ming, I opted to keep your Reviewed-by since the change since v1 was trivial.
Hope that's okay.
---
drivers/block/loop.c | 9 +++--
1 file changed, 7 insertions(+), 2 dele
On Wed, Feb 6, 2019 at 1:33 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-02-05 10:59:01)
> > diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c
> > b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c
> > index aef40f7a41d4..b05f89d734f0 100644
> > --- a/dri
On Mon, Jan 21, 2019 at 4:25 PM Rob Herring wrote:
>
> On Fri, Jan 11, 2019 at 03:01:24PM -0800, Evan Green wrote:
> > Wire up the reset controller in the Qcom UFS controller for the PHY.
> > This will be used to toggle PHY reset during initialization of the PHY.
> >
>
On Wed, Jan 16, 2019 at 1:29 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-11 15:01:23)
> > diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> > b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> > index 21d9a93db2e97..985f5e99ab332 100644
On Fri, Jan 18, 2019 at 2:31 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-11 15:01:26)
> > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
> > index 3aeadb14aae1e..db46f9a64b54c 100644
> > --- a/drivers/scsi/ufs/ufs-qcom.c
> > +++
On Fri, Jan 18, 2019 at 2:33 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-11 15:01:27)
> > @@ -1214,6 +1225,32 @@ static int qcom_qmp_phy_init(struct phy *phy)
> >
> > dev_vdbg(qmp->dev, "Initializing QMP phy\n");
>
On Fri, Jan 18, 2019 at 2:39 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-11 15:01:28)
> > For UFS, move the actual firing up of the PHY to phy_poweron and
> > phy_poweroff callbacks, rather than init/exit. UFS calls
> > phy_poweroff during suspend, so now all c
On Fri, Jan 18, 2019 at 3:50 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-11 15:01:29)
> > diff --git a/drivers/phy/qualcomm/phy-qcom-ufs.c
> > b/drivers/phy/qualcomm/phy-qcom-ufs.c
> > index f2979ccad00a3..a4cff17fef925 100644
> > --- a/drivers/phy/qua
is mapped back in user land to
> the applicable sg_io_v4 xferp: dout_xferp for write descriptor,
> and din_xferp for read descriptor.
>
> Signed-off-by: Avri Altman
Reviewed-by: Evan Green
On Mon, Jan 14, 2019 at 9:08 AM Doug Anderson wrote:
>
> Hi,
>
> On Fri, Jan 11, 2019 at 7:37 PM Martin K. Petersen
> wrote:
> >
> >
> > Evan,
> >
> > > CONFIG_SCSI_UFS_QCOM selects CONFIG_PHY_QCOM_UFS, assuming that
> > > this was the only possible PHY driver Qualcomm's UFS controller
> > > woul
lected, and
Qualcomm platforms except for SDM845 need it.
Fixes: 326a859b2814 ("scsi: ufs: Remove select of phy-qcom-ufs from ufs-qcom")
Signed-off-by: Evan Green
---
I unfortunately don't have a non-SDM845 device to test this on. I'm hoping
it Just Works, or someone might be will
On Mon, Jan 14, 2019 at 10:41 AM Evan Green wrote:
>
> On Mon, Jan 14, 2019 at 9:08 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Fri, Jan 11, 2019 at 7:37 PM Martin K. Petersen
> > wrote:
> > >
> > >
> > > Evan,
> > >
msg)
> if (rpm_msg->needs_free)
>
>
> Let's fix this by allocating a chunk of completions for each message and
> waiting for all of them to be completed before returning from the batch
> API. Alternatively, we could wait for the last message in the bat
On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse wrote:
>
> Try to get the interconnect path for the GPU and vote for the maximum
> bandwidth to support all frequencies. This is needed for performance.
> Later we will want to scale the bandwidth based on the frequency to
> also optimize for power bu
On Fri, Jan 18, 2019 at 3:27 PM Jordan Crouse wrote:
>
> On Fri, Jan 18, 2019 at 03:04:34PM -0800, Evan Green wrote:
> > On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse
> > wrote:
> > >
> > > Try to get the interconnect path for the GPU and vote for the ma
On Thu, Jan 31, 2019 at 3:31 PM Bart Van Assche wrote:
>
> On Thu, 2019-01-31 at 14:13 -0800, Evan Green wrote:
> > diff --git a/drivers/block/loop.c b/drivers/block/loop.c
> > index cf5538942834..a1ba555e3b92 100644
> > --- a/drivers/block/loop.c
> > +++ b/driv
uduru1
...weird that there's a 1 in your name.
> Signed-off-by: Jayant Shekhar
Reviewed-by: Evan Green
On Thu, Dec 20, 2018 at 10:29 PM Jayant Shekhar wrote:
>
> Add interconnect properties such as the source and the destination
> ports for MDSS on SDM845.
>
> Signed-off-by: Jayant Shekhar
Reviewed-by: Evan Green
Stephen).
- Remove include of reset.h (Stephen)
- Fix error print of phy_power_on (Stephen)
- Comment for reset controller warnings on id != 0 (Stephen)
- Add static to ufs_qcom_reset_ops (Stephen).
- Use devm_* to get the reset (Stephen)
- Clear ufs_reset on error getting it
- Remove needless error pri
Enable Qualcomm UFS controllers to expose the PHY reset via a reset
controller.
Signed-off-by: Evan Green
---
Fixing up this aspect of it made me notice that this patch [1]
hasn't landed yet. It really ought to.
[1]
https://lore.kernel.org/lkml/20181012213926.253765-1-diand...@chromium.
through the PHY framework.
Signed-off-by: Evan Green
Reviewed-by: Rob Herring
---
Changes in v2:
- Added resets to example (Stephen).
Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
on in suspend that shouldn't
be.
This new scheme gives the UFS reset to the PHY, so that it can fully
initialize itself in a single callback. We can then turn regulators on
during poweron and off during poweroff.
Signed-off-by: Evan Green
Reviewed-by: Rob Herring
---
I realize I'm no
Request the newly minted reset controller from the Qualcomm UFS
controller, and use it to toggle the PHY reset line from within
the PHY. This will allow us to merge the two phases of UFS PHY
initialization.
Signed-off-by: Evan Green
---
Note: this change is dependent on the previous changes
Add the reset controller for the UFS controller, and wire it up
so that the UFS PHY can initialize itself without relying on
implicit sequencing between the two drivers.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
---
Changes in v2: None
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4
Expose a reset controller that the phy can use to perform its
initialization in a single callback.
Also, change the use of the phy functions from ufs-qcom such that
phy_poweron actually fires up the phy, and phy_poweroff actually
powers it down.
Signed-off-by: Evan Green
---
Note: This change
For UFS, move the actual firing up of the PHY to phy_poweron and
phy_poweroff callbacks, rather than init/exit. UFS calls
phy_poweroff during suspend, so now all clocks and regulators for
the phy can be powered down during suspend.
Signed-off-by: Evan Green
---
Changes in v2:
- Removed
in poweron, but only
poweroff is called during suspend, not exit.
Consolidate the initialization code into phy_poweron, and utilize
the reset controller exported from the UFS driver to explicitly
perform all the steps needed to initialize the PHY.
Signed-off-by: Evan Green
---
Changes in v2:
- Use de
Wire up the reset controller in the Qcom UFS controller for the PHY.
This will be used to toggle PHY reset during initialization of the PHY.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
---
This commit is based atop the series at [1]. Patches 1 and 2 of that
series have landed, but 3, 4
On Thu, Oct 18, 2018 at 12:52 AM Vivek Gautam
wrote:
>
...
>
> Yes, this patch is good to go.
>
I don't think this patch ever got picked up, despite being reviewed
and good to go. Can it be applied somewhere?
-Evan
On Mon, Jan 21, 2019 at 10:34 PM Alok Chauhan wrote:
>
> Add documentation for the interconnect and interconnect-names bindings
> for the GENI QUP as detailed by bindings/interconnect/interconnect.txt.
>
> Signed-off-by: Alok Chauhan
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,geni-s
On Mon, Jan 21, 2019 at 10:34 PM Alok Chauhan wrote:
>
> Get the interconnect paths for I2C based Serial Engine device
> and vote accordingly based on maximum supported I2C frequency.
>
> Signed-off-by: Alok Chauhan
> ---
> drivers/i2c/busses/i2c-qcom-geni.c | 13 +
> 1 file changed,
On Mon, Jan 21, 2019 at 10:34 PM Alok Chauhan wrote:
>
> Get the interconnect paths for SPI based Serial Engine device
> and vote accordingly based on maximum supported SPI frequency.
>
> Signed-off-by: Alok Chauhan
> ---
> drivers/spi/spi-geni-qcom.c | 20 +++-
> 1 file changed,
On Wed, Jan 23, 2019 at 11:02 PM Asutosh Das wrote:
>
> Adapt to the new ICB framework for bus bandwidth voting.
>
> This requires the source/destination port ids.
> Also this requires a tuple of values.
>
> The tuple is for two different paths - from UFS master
> to BIMC slave. The other is from
On Tue, May 7, 2019 at 3:14 PM Pierre-Louis Bossart
wrote:
>
> Minor nit-picks below. The Kconfig would work but select CANNONLAKE even
> if you don't want it.
>
> >
> > +config SND_SOC_SOF_COMETLAKE_LP
> > + tristate
> > + select SND_SOC_SOF_CANNONLAKE
>
> This should be
> select SND_SOF_
On Tue, May 7, 2019 at 3:31 PM Pierre-Louis Bossart
wrote:
>
> On 5/7/19 4:53 PM, Evan Green wrote:
> > Add PCI IDs for Intel CometLake platforms, which from a software
> > point of view are extremely similar to Cannonlake platforms.
>
> Humm, I have mixed feelings here.
On Wed, May 8, 2019 at 10:00 AM Pierre-Louis Bossart
wrote:
>
>
>
> On 5/8/19 11:42 AM, Evan Green wrote:
> > On Tue, May 7, 2019 at 3:14 PM Pierre-Louis Bossart
> > wrote:
> >>
> >> Minor nit-picks below. The Kconfig would work but select
On Wed, May 8, 2019 at 10:04 AM Pierre-Louis Bossart
wrote:
>
>
>
> On 5/8/19 11:51 AM, Evan Green wrote:
> > On Tue, May 7, 2019 at 3:31 PM Pierre-Louis Bossart
> > wrote:
> >>
> >> On 5/7/19 4:53 PM, Evan Green wrote:
> >>> Add PCI ID
of_match_table regardless
of whether CONFIG_OF is enabled or not, since the table is used by
ACPI for PRP0001 devices.
Signed-off-by: Evan Green
---
drivers/platform/chrome/cros_ec_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/chrome/cros_ec_spi.c
b/drivers
Add support for Intel Comet Lake platforms by adding a new Kconfig
for CometLake and the appropriate PCI IDs.
Signed-off-by: Evan Green
---
Changes in v3:
- Copy cnl_desc to new cml_desc, and avoid selecting cannonlake (Pierre-Louis)
Changes in v2:
- Add CML-H ID 0x06c8 (Pierre-Louis)
sound
Add PCI IDs for Intel CometLake platforms, which from a software
point of view are extremely similar to Cannonlake platforms.
Signed-off-by: Evan Green
---
Changes in v3:
- Don't select CML_* in SND_SOC_INTEL_SKYLAKE (Pierre-Louis)
Changes in v2:
- Add 0x06c8 for CML-H (Pierre-Louis)
erre-Louis)
Changes in v2:
- Add CML-H ID 0x06c8 (Pierre-Louis)
- Add 0x06c8 for CML-H (Pierre-Louis)
Evan Green (2):
ASoC: SOF: Add Comet Lake PCI IDs
ASoC: Intel: Skylake: Add Cometlake PCI IDs
sound/soc/intel/Kconfig| 16 +
sound/soc/intel/skylake/skl-messa
On Mon, May 20, 2019 at 7:44 AM Alex Elder wrote:
>
> On 5/20/19 9:43 AM, Arnd Bergmann wrote:
> > I have no idea how two 8-bit assignments could do that,
> > it sounds like a serious gcc bug, unless you mean two
> > 8-byte assignments, which would be within the range
> > of expected behavior. If
On Mon, May 20, 2019 at 9:50 AM Alex Elder wrote:
>
> On 5/20/19 11:34 AM, Evan Green wrote:
> > On Mon, May 20, 2019 at 7:44 AM Alex Elder wrote:
> >>
> >> On 5/20/19 9:43 AM, Arnd Bergmann wrote:
> >>> I have no idea how two 8-bit assignments could d
On Fri, Apr 5, 2019 at 12:28 AM Rajneesh Bhardwaj
wrote:
>
> On Mon, Apr 01, 2019 at 11:05:04AM -0700, Evan Green wrote:
> > The PMC driver performs a 32-bit read on the sleep s0 residency counter,
> > followed by a hard-coded multiplication to convert into microseconds.
>
dev's write_zeroes into loopdev's discard_sectors.
Changes in v3:
- Updated tags
- Updated commit description
Changes in v2:
- Unnested error if statement (Bart)
Evan Green (2):
loop: Report EOPNOTSUPP properly
loop: Better discard support for block devices
drivers/bl
Add PCI IDs for Intel CometLake platforms, which from a software
point of view are extremely similar to Cannonlake platforms.
Signed-off-by: Evan Green
---
sound/soc/intel/Kconfig| 9 +
sound/soc/intel/skylake/skl-messages.c | 8
sound/soc/intel/skylake/skl.c
On Mon, May 6, 2019 at 3:53 PM Evan Green wrote:
>
>
> This small series adds PCI IDs for Cometlake platforms, for a
> dazzling audio experience.
>
>
> Evan Green (2):
> ASoC: SOF: Add Comet Lake PCI ID
> ASoC: Intel: Skylake: Add Cometlake PCI IDs
&
This small series adds PCI IDs for Cometlake platforms, for a
dazzling audio experience.
Evan Green (2):
ASoC: SOF: Add Comet Lake PCI ID
ASoC: Intel: Skylake: Add Cometlake PCI IDs
sound/soc/intel/Kconfig| 9 +
sound/soc/intel/skylake/skl-messages.c | 8
Add support for Intel Comet Lake platforms by adding a new Kconfig
for CometLake and the appropriate PCI ID.
Signed-off-by: Evan Green
---
sound/soc/sof/intel/Kconfig | 16
sound/soc/sof/sof-pci-dev.c | 4
2 files changed, 20 insertions(+)
diff --git a/sound/soc/sof
On Tue, May 7, 2019 at 1:26 PM Pierre-Louis Bossart
wrote:
>
>
>
> > On 5/6/19 5:53 PM, Evan Green wrote:
> >>> Add support for Intel Comet Lake platforms by adding a new Kconfig for
> >>> CometLake and the appropriate PCI ID.
> >
> >> This
This small series adds PCI IDs for Cometlake platforms, for a
dazzling audio experience.
Changes in v2:
- Add CML-H ID 0x06c8 (Pierre-Louis)
- Add 0x06c8 for CML-H (Pierre-Louis)
Evan Green (2):
ASoC: SOF: Add Comet Lake PCI IDs
ASoC: Intel: Skylake: Add Cometlake PCI IDs
sound/soc/intel
Add support for Intel Comet Lake platforms by adding a new Kconfig
for CometLake and the appropriate PCI IDs.
Signed-off-by: Evan Green
---
Changes in v2:
- Add CML-H ID 0x06c8 (Pierre-Louis)
sound/soc/sof/intel/Kconfig | 32
sound/soc/sof/sof-pci-dev.c | 8
Add PCI IDs for Intel CometLake platforms, which from a software
point of view are extremely similar to Cannonlake platforms.
Signed-off-by: Evan Green
---
Changes in v2:
- Add 0x06c8 for CML-H (Pierre-Louis)
sound/soc/intel/Kconfig| 18 ++
sound/soc/intel
s an extraneous
error print in block/013 when testing on a loop device backed
by a block device that does not support discard.
Signed-off-by: Evan Green
---
Changes in v4:
- Mirror blkdev's write_zeroes into loopdev's discard_sectors.
Changes in v3:
- Updated commit description
Chan
> > ---
> > - update i2c info
> > drivers/mfd/intel-lpss-pci.c | 13 +
> > 1 file changed, 13 insertions(+)
> >
> Reviewed-by: Jarkko Nikula
Tested-by: Evan Green
Hi Georgi and David,
On Tue, Jun 18, 2019 at 2:17 AM Georgi Djakov wrote:
>
> Consumers may have use cases with different bandwidth requirements based
> on the system or driver state. The consumer driver can append a specific
> tag to the path and pass this information to the interconnect platfor
Hi Georgi and David,
On Tue, Jun 18, 2019 at 2:17 AM Georgi Djakov wrote:
>
> From: David Dai
>
> Add support for wake and sleep commands by using a tag to indicate
> whether or not the aggregate and set requests fall into execution
> state specific bucket.
>
> Signed-off-by: David Dai
> Signed
On Mon, Jul 1, 2019 at 6:41 AM Enric Balletbo i Serra
wrote:
>
>
>
> On 1/7/19 8:01, Lee Jones wrote:
> > On Thu, 27 Jun 2019, Enric Balletbo Serra wrote:
> >
> >> Hi Evan, Lee,
> >>
> >> Missatge de Evan Green del dia dj., 27 de juny
> &g
On Fri, Jul 12, 2019 at 10:04 AM Evan Green wrote:
>
> On Mon, Jul 1, 2019 at 6:41 AM Enric Balletbo i Serra
> wrote:
> >
> >
> >
> > On 1/7/19 8:01, Lee Jones wrote:
> > > On Thu, 27 Jun 2019, Enric Balletbo Serra wrote:
> > >
> > >&
> Signed-off-by: Georgi Djakov
Reviewed-by: Evan Green
Hi Sibi,
On Wed, Aug 7, 2019 at 4:24 AM Sibi Sankar wrote:
>
> On some Qualcomm SoCs, Operating State Manager (OSM) controls the
> resources of scaling L3 caches. Add a driver to handle bandwidth
> requests to OSM L3 from CPU/GPU.
>
> Signed-off-by: Sibi Sankar
This looks good to me, just a cou
river to do the aggregation based on this state.
>
> Introduce icc_set_tag() function that will allow the consumers to append
> an optional tag to each path. The aggregation of these tagged paths is
> platform specific.
>
> Signed-off-by: Georgi Djakov
Reviewed-by: Evan Green
of this for now is that it will significantly simplify the code
> in provider drivers.
>
> Suggested-by: Evan Green
> Signed-off-by: Georgi Djakov
Reviewed-by: Evan Green
On Fri, Aug 9, 2019 at 5:13 AM Georgi Djakov wrote:
>
> From: David Dai
>
> Add support for wake and sleep commands by using a tag to indicate
> whether or not the aggregate and set requests fall into execution
> state specific bucket.
>
> Signed-off-by: David Dai
> Signed-off-by: Georgi Djakov
On Tue, Jul 30, 2019 at 5:37 PM David Dai wrote:
>
>
> On 7/30/2019 3:54 PM, Evan Green wrote:
> > On Thu, Jul 18, 2019 at 10:59 AM David Dai wrote:
> >> On 7/16/2019 1:15 PM, Evan Green wrote:
> >>> On Mon, Jul 15, 2019 at 4:34 PM David Dai
> >>
of this for now is that it will significantly simplify the code
> in provider drivers.
>
> Suggested-by: Evan Green
> Signed-off-by: Georgi Djakov
Thanks Georgi, I like it! We should confirm that it actually does
allow David to remove the sum_avg_cached and max_peak_cached sh
On Thu, Jul 18, 2019 at 10:59 AM David Dai wrote:
>
> On 7/16/2019 1:15 PM, Evan Green wrote:
> > On Mon, Jul 15, 2019 at 4:34 PM David Dai wrote:
> >> Hi Evan,
> >>
> >> Thanks for the continued help in reviewing these patches!
> > No problem. I want
For ECs that support it, the EC returns the number of slp_s0
transitions and whether or not there was a timeout in the resume
response. Expose the last resume result to usermode via debugfs so
that usermode can detect and report S0ix timeouts.
Signed-off-by: Evan Green
---
Changes in v2
901 - 1000 of 1193 matches
Mail list logo
