On Sun, Feb 17, 2019 at 1:08 AM Yong Wu <yong...@mediatek.com> wrote: > > In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is > REG_MMU_CTRL in the other SoCs, and the bits meaning is completely > different with the REG_MMU_STANDARD_AXI_MODE. > > This patch moves this property to plat_data, it's also a preparing > patch for mt8183. > > Signed-off-by: Yong Wu <yong...@mediatek.com> > Reviewed-by: Nicolas Boichat <drink...@chromium.org>
Reviewed-by: Evan Green <evgr...@chromium.org>
