On Fri, May 26, 2017 at 08:33:54PM -0700, John Stultz wrote:
> From: Will Deacon
>
> Commit 45a7905fc48f ("arm64: vdso: defer shifting of nanosecond
> component of timespec") fixed sub-ns inaccuracies in our vDSO
> clock_gettime implementation by deferring the right-s
Hi Sunil,
On Mon, May 29, 2017 at 02:41:59PM +0530, Sunil Kovvuri wrote:
> On Fri, May 5, 2017 at 4:47 PM, wrote:
> > From: Sunil Goutham
> >
> > Processing queue full of TLB invalidation commands might
> > take more time on some platforms than current timeout
> > of 100us. So increased drain t
On Mon, May 29, 2017 at 06:18:45PM -0700, Ray Jui wrote:
> I'm writing to check with you to see if the latest arm-smmu.c driver in
> v4.12-rc Linux for smmu-500 can support mapping that is only specific to
> a particular physical address range while leave the rest still to be
> handled by the clien
On Tue, Oct 31, 2017 at 12:43:19PM +0100, Jason A. Donenfeld wrote:
> Versions of gcc prior to gcc 5 emitted a __multi3 function call when
> dealing with TI types, resulting in failures when trying to link to
> libgcc, and more generally, horrible performance. However, since gcc 5,
> the compiler s
Hi Jason,
On Tue, Oct 31, 2017 at 12:57:29PM +0100, Jason A. Donenfeld wrote:
> On Tue, Oct 31, 2017 at 12:51 PM, Will Deacon wrote:
> > Which code in the kernel actually uses 128-bit types directly? I know we
> > have some unfortunate occurences in our headers (includin
On Tue, Oct 31, 2017 at 06:04:19PM -0400, Jon Masters wrote:
> On 10/31/2017 02:30 PM, Mark Salyzyn wrote:
> > Take an effort to recode the arm64 vdso code from assembler to C
> > previously submitted by Andrew Pinski , rework
> > it for use in both arm and arm64, overlapping any optimizations
> >
PEI: Remove arch_apei_flush_tlb_one()
>
> arch/arm64/include/asm/acpi.h | 12 --
> arch/arm64/include/asm/fixmap.h | 5 +++
> arch/arm64/mm/mmu.c | 4 ++
If you need it:
Acked-by: Will Deacon
for the arm64 bits.
Will
Hi Jason,
On Tue, Oct 31, 2017 at 12:43:19PM +0100, Jason A. Donenfeld wrote:
> Versions of gcc prior to gcc 5 emitted a __multi3 function call when
> dealing with TI types, resulting in failures when trying to link to
> libgcc, and more generally, horrible performance. However, since gcc 5,
> the
On Thu, Nov 02, 2017 at 01:08:52PM -0400, Alan Stern wrote:
> On Thu, 2 Nov 2017, Peter Zijlstra wrote:
>
> > On Thu, Nov 02, 2017 at 11:40:35AM -0400, Alan Stern wrote:
> > > On Thu, 2 Nov 2017, Peter Zijlstra wrote:
> > >
> > > > > Lock functions such as refcount_dec_and_lock() &
> > > > > refc
Hi Dave,
[+linux-arm-kernel]
On Tue, Oct 31, 2017 at 03:31:46PM -0700, Dave Hansen wrote:
> KAISER makes it harder to defeat KASLR, but makes syscalls and
> interrupts slower. These patches are based on work from a team at
> Graz University of Technology posted here[1]. The major addition is
>
On Tue, Oct 24, 2017 at 11:25:12AM +0200, Ingo Molnar wrote:
>
> * Paul E. McKenney wrote:
>
> > From: Will Deacon
> >
> > linux/compiler.h is included indirectly by linux/types.h via
> > uapi/linux/types.h -> uapi/linux/posix_types.h -> linux/stddef.h
&
On Tue, Oct 24, 2017 at 11:31:04AM +0200, Ingo Molnar wrote:
>
> * Paul E. McKenney wrote:
>
> > From: Will Deacon
> >
> > lockless_dereference is a nice idea, but its gained little traction in
> > kernel code since it's introduction three years ago. Thi
enney"
Signed-off-by: Will Deacon
---
include/linux/compiler.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 08083186e54f..7d7b77da9716 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -242,6 +242,7
uapi/linux/stddef.h and linux/linkage.h are then moved over to include
linux/compiler_types.h, which fixes the build for h8 and blackfin.
Cc: Ingo Molnar
Cc: "Paul E. McKenney"
Signed-off-by: Will Deacon
---
arch/arm/include/asm/ptrace.h | 3 +-
arch/sparc/include/asm/ptrace.h |
Hi Ingo, Paul,
Here's another spin of the patches removing lockless_dereference(), taking
into account Ingo's review comments.
Thanks,
Will
--->8
Will Deacon (5):
linux/compiler.h: Split into compiler.h and compiler_types.h
locking/barriers: Add implicit smp_read_barrier
y"
Signed-off-by: Will Deacon
---
Documentation/memory-barriers.txt| 12
Documentation/translations/ko_KR/memory-barriers.txt | 12
include/linux/compiler.h | 20
3 files changed, 44 deletions(-
READ_ONCE() now has an implicit smp_read_barrier_depends() call, so it
can be used instead of lockless_dereference() without any change in
semantics.
Cc: Ingo Molnar
Cc: "Paul E. McKenney"
Signed-off-by: Will Deacon
---
arch/x86/events/core.c | 2 +-
arch/x86/i
On Tue, Oct 24, 2017 at 11:54:28AM +0200, Ingo Molnar wrote:
> * Will Deacon wrote:
> > On Tue, Oct 24, 2017 at 11:31:04AM +0200, Ingo Molnar wrote:
> > > Also, could we please split this into three patches:
> > >
> > > #1: Add smp_read_barrier_depends() t
anything to enforce dependency
ordering.
Signed-off-by: Will Deacon
Signed-off-by: Paul E. McKenney
---
arch/alpha/include/asm/atomic.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h
index 498933a7df97..16961a3f45ba
gt; Signed-off-by: Mark Salyzyn
> Cc: Kees Cook
> Cc: Anton Vorontsov
> Cc: Tony Luck
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Anton Vorontsov
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> v2:
> - simplify, do
On Tue, Oct 24, 2017 at 03:04:04AM -0500, Kim Phillips wrote:
> Introduce new tools/perf/arch/*/util/evsel.c:perf_evsel__suppl_strerror()
> so each arch can start to customize usability for its h/w PMU drivers.
>
> Signed-off-by: Kim Phillips
> ---
> tools/perf/arch/x86/util/Build | 1 +
> to
On Tue, Oct 24, 2017 at 03:04:15AM -0500, Kim Phillips wrote:
> Use the Arm CCN driver as an example of how to try to improve
> upon its existing dmesg error output, and duplicate error string
> generation logic in the perf tool.
[...]
> Comments? Is this really that much better than the existin
On Tue, Oct 24, 2017 at 03:04:08AM -0500, Kim Phillips wrote:
> Call perf_evsel__open_strerror() to potentially expand upon why the
> event was "not supported by the kernel." See the enhanced '-v' example
> output messages in the next patch.
Nit: it would be better if the commit message was self-
Hi Palmer,
Some late comments on this which you might want to address as you get the
chance.
On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
> This contains all the code that directly interfaces with the RISC-V
> memory model. While this code corforms to the current RISC-V ISA
>
Ingo, Peter,
Would you be willing to merge this via -tip, please? I'm happy to
rebase/repost as required, but the code is in good shape now.
Will
On Thu, Oct 19, 2017 at 05:53:32PM +0100, Will Deacon wrote:
> On Thu, Oct 12, 2017 at 01:20:46PM +0100, Will Deacon wrote:
> > This is
---
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 8
> 1 file changed, 8 insertions(+)
Thanks. Without this patch, memtest dies early on at physical address
0x0510 due to an SError. With the patch, things work well, so:
Acked-by: Will Deacon
Tested-by: Will Deacon
Please als
On Tue, Nov 07, 2017 at 04:31:17PM +1100, Stephen Rothwell wrote:
> Hi Catalin,
>
> Commit
>
> 2c0db5b45071 ("rm64: Implement __lshrti3 library function")
>
> is missing a Signed-off-by from its author.
Bugger; my fault. I split Jason's patch in a hurry so that it applied on
top of his old on
Hi Palmer,
On Mon, Nov 13, 2017 at 01:56:22PM -0800, Palmer Dabbelt wrote:
> The following changes since commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4:
>
> Linux 4.14 (2017-11-12 10:46:13 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/
ulose (4):
arm64: Expose support for optional ARMv8-A features
arm64: Fix the feature type for ID register fields
perf: arm_spe: Prevent module unload while the PMU is in use
arm-ccn: perf: Prevent module unload while PMU is in use
Thomas Meyer (1):
arm64: dma-mapping:
;
> Fixes: commit a33b0daab73a0 ("bus: ARM CCN PMU driver")
nit: don't need "commit" here.
> Cc: Pawel Moll
> Cc: Will Deacon
> Cc: Mark Rutland
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/bus/arm-ccn.c | 1 +
> 1 file changed, 1 ins
On Thu, Nov 02, 2017 at 12:38:05PM -0700, Dave Hansen wrote:
> On 11/02/2017 12:01 PM, Will Deacon wrote:
> > On Tue, Oct 31, 2017 at 03:31:46PM -0700, Dave Hansen wrote:
> >> KAISER makes it harder to defeat KASLR, but makes syscalls and
> >> interrupts slower. Thes
Hi Jason,
[+Ard]
On Thu, Nov 02, 2017 at 06:43:22PM +0100, Jason A. Donenfeld wrote:
> Versions of gcc prior to gcc 5 emitted a __multi3 function call when
> dealing with TI types, resulting in failures when trying to link to
> libgcc, and more generally, bad performance. However, since gcc 5,
>
On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
> On 17/10/2017 13:59, Will Deacon wrote:
> >Hi Shaokun,
> >
> >Thanks for the patch. One comment below.
> >
> >On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
> >>This is a short
y calls local_irq_save(flags)), switch it over to
arch_spin_lock and get things building again.
Cc: Peter Zijlstra
Reported-by: kbuild test robot
Signed-off-by: Will Deacon
---
This patch fixes build breakage in -next via the -tip tree.
arch/powerpc/kernel/rtas.c | 2 +-
1 file changed, 1
On Tue, Sep 12, 2017 at 09:00:37PM +0800, Zhen Lei wrote:
> This patch is base on:
> (add02cfdc9bc2 "iommu: Introduce Interface for IOMMU TLB Flushing")
>
> Because iotlb_sync is moved out of ".unmap = arm_smmu_unmap", some interval
> ".unmap" calls should explicitly followed by a iotlb_sync oper
Hi Thunder,
On Tue, Sep 12, 2017 at 09:00:36PM +0800, Zhen Lei wrote:
> Because all TLBI commands should be followed by a SYNC command, to make
> sure that it has been completely finished. So we can just add the TLBI
> commands into the queue, and put off the execution until meet SYNC or
> other c
Hi Ganapat,
On Thu, Sep 21, 2017 at 02:29:18PM +0530, Ganapatrao Kulkarni wrote:
> Adding numa aware memory allocations used for iommu dma allocation and
> memory allocated for SMMU stream tables, page walk tables and command queues.
>
> With this patch, iperf testing on ThunderX2, with 40G NIC c
On Tue, Oct 17, 2017 at 01:55:16PM +0100, Mark Rutland wrote:
> On Tue, Oct 17, 2017 at 12:38:14PM +0100, Will Deacon wrote:
> > On Tue, Oct 17, 2017 at 12:10:33PM +0100, Mark Rutland wrote:
> > > On Tue, Oct 17, 2017 at 11:58:58AM +0100, Will Deacon wrote:
> > > >
Hi John,
On Wed, Oct 18, 2017 at 05:37:03PM +0100, John Garry wrote:
> On 18/10/2017 11:49, Will Deacon wrote:
> >On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
> >>On 17/10/2017 13:59, Will Deacon wrote:
> >>>On Tue, Oct 17, 2017 at 03:01:39PM +0800, S
On Wed, Oct 18, 2017 at 01:03:10PM -0400, Pavel Tatashin wrote:
> I asked Will, about it, and he preferred to have this patched added to the
> end of my series instead of replacing "arm64/kasan: add and use
> kasan_map_populate()".
As I said, I'm fine either way, I just didn't want to cause extra
On Thu, Oct 19, 2017 at 11:00:45AM +0800, Leizhen (ThunderTown) wrote:
>
>
> On 2017/10/18 20:58, Will Deacon wrote:
> > Hi Thunder,
> >
> > On Tue, Sep 12, 2017 at 09:00:36PM +0800, Zhen Lei wrote:
> >> Because all TLBI commands should be followed by a SYN
;
> Did I get that right? If I have the wrong patches or am missing some
> dependencies, please let me know. Otherwise, I will create a branch
> including available patches from 1-3 and 5 above.
>
> Are people comfortable with my pushing the straightforward stuff
> (that is, excluding #5 and #6) into the next merge window?
That works for me, and you can have my Ack if you need it:
Acked-by: Will Deacon
Will
On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote:
> Will, are you happy to queue this?
>
> There's a minor fixup [1] needed in patch 2, but otherwise this looks
> good to me, and builds cleanly.
>
> I've pushed out a branch [2] with that fix folded in, in case that's
> easier for you.
Hi all,
On Thu, Oct 12, 2017 at 01:20:46PM +0100, Will Deacon wrote:
> This is version three of the patches previously posted here:
>
> v1:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/534666.html
> v2:
> http://lists.infradead.org/pipermail/lin
On Thu, Oct 26, 2017 at 10:09:40AM +0100, Mark Rutland wrote:
> Hi,
>
> In Prague, Kees mentioned that it would be nice to have a mechanism to
> catch bad __{get,put}_user uses, such as the recent CVE-2017-5123 [1,2]
> issue with unsafe_put_user() in waitid().
>
> These patches allow an optional
On Fri, Oct 27, 2017 at 09:33:41AM -0700, Nick Desaulniers wrote:
> Upon upgrading to binutils 2.27, we found that our lz4 and gzip
> compressed kernel images were significantly larger, resulting is 10ms
> boot time regressions.
>
> As noted by Rahul:
> "aarch64 binaries uses RELA relocations, whe
On Mon, Oct 30, 2017 at 01:11:23PM +, Ard Biesheuvel wrote:
> On 30 October 2017 at 13:08, Will Deacon wrote:
> > On Fri, Oct 27, 2017 at 09:33:41AM -0700, Nick Desaulniers wrote:
> >> Upon upgrading to binutils 2.27, we found that our lz4 and gzip
> >> co
On Mon, Oct 30, 2017 at 01:35:49PM +, Ard Biesheuvel wrote:
> On 30 October 2017 at 13:12, Will Deacon wrote:
> > On Mon, Oct 30, 2017 at 01:11:23PM +, Ard Biesheuvel wrote:
> >> On 30 October 2017 at 13:08, Will Deacon wrote:
> >> > On Fri, Oct 27,
Hi Mark,
On Thu, Oct 12, 2017 at 04:01:45PM -0700, Mark Salyzyn wrote:
> Add a case for CLOCK_BOOTTIME as it is popular for measuring
> relative time on systems expected to suspend() or hibernate().
>
> Signed-off-by: Mark Salyzyn
>
> v2: rebased and changed from 3/3 to 10/10, fortified commit
On Mon, Oct 30, 2017 at 10:46:31AM -0700, Linus Torvalds wrote:
> On Mon, Oct 30, 2017 at 10:20 AM, Linus Torvalds
> wrote:
> >
> > I will add a "might_sleep()" to ioremap_page_range() itself, so that
> > we get this warning more reliably and much eailer. Right now it has
> > been hidden by the fa
On Mon, Oct 30, 2017 at 09:44:35PM +, Mark Rutland wrote:
> On Mon, Oct 30, 2017 at 01:34:13PM -0700, Mark Salyzyn wrote:
> > On 10/30/2017 07:18 AM, Mark Rutland wrote:
> > > On Fri, Oct 27, 2017 at 03:23:48PM -0700, Mark Salyzyn wrote:
> > > > Note I noticed a bug in the old implementation of
On Mon, Oct 30, 2017 at 04:14:15PM -0400, Tyler Baicar wrote:
> On 10/30/2017 1:46 PM, Linus Torvalds wrote:
> >On Mon, Oct 30, 2017 at 10:20 AM, Linus Torvalds
> > wrote:
> >>I will add a "might_sleep()" to ioremap_page_range() itself, so that
> >>we get this warning more reliably and much eailer.
Hi Drew,
On Thu, Oct 01, 2015 at 06:26:47PM +0100, Drew Richardson wrote:
> I got some undeliverable responses the first time, sorry if you get this twice
>
> ---
>
> The layout of stack frames has changed over time. Testing using a
> arm-linux-gnueabi gcc-4.2 from 2007 the original code didn't
On Mon, Oct 05, 2015 at 03:07:57AM +, Sarbojit Ganguly wrote:
> This is my second version of the patch which covers the byte exclusive
> case as pointed out by you.
> Please share your opinion on this.
The patch you posted is corrupted (the whitespace looks completely off)
so it can't be appli
On Thu, Oct 01, 2015 at 07:03:01PM +0100, Paul E. McKenney wrote:
> On Thu, Oct 01, 2015 at 07:13:04PM +0200, Peter Zijlstra wrote:
> > On Thu, Oct 01, 2015 at 08:09:09AM -0700, Paul E. McKenney wrote:
> > > On Thu, Oct 01, 2015 at 02:24:40PM +0200, Peter Zijlstra wrote:
> >
> > > > I must say I'm
ard code to cover the byte exchange case as
> well following opinion of Will Deacon.
> Checkpatch has been run and issues were taken care of.
>
> Since support for half-word atomic exchange was not there and Qspinlock
> on ARM requires it, modified __xchg() to add support for that
On Thu, Oct 01, 2015 at 07:39:10AM +0100, Peter Zijlstra wrote:
> On Wed, Sep 30, 2015 at 01:03:11PM -0700, Davidlohr Bueso wrote:
> > Similar to what we have for regular add/sub calls. For now, no actual arch
> > implements them, so everyone falls back to the default atomics... iow,
> > nothing ch
On Mon, Oct 05, 2015 at 09:48:24PM +0200, Peter Zijlstra wrote:
> On Mon, Oct 05, 2015 at 06:32:43PM +0100, Will Deacon wrote:
> > On Thu, Oct 01, 2015 at 07:39:10AM +0100, Peter Zijlstra wrote:
> > > On Wed, Sep 30, 2015 at 01:03:11PM -0700, Davidlohr Bueso wrote:
> > >
On Tue, Oct 06, 2015 at 11:05:43AM +0530, Manjeet Pawar wrote:
> MINSIGSTKSZ and SIGSTKSZ for ARM64 are not correctly set in latest kernel.
> This patch fixes this issue.
>
> This issue is reported in LTP (testcase: sigaltstack02.c).
> Testcase failed when sigaltstack() called with stack size "MIN
On Tue, Oct 06, 2015 at 08:03:02AM +, Sarbojit Ganguly wrote:
> Here is the version 3 of the patch correcting earlier issues.
This looks good to me now:
Acked-by: Will Deacon
> v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
> #ifndef.
> v1 ->
On Tue, Oct 06, 2015 at 06:24:23PM +0200, Peter Zijlstra wrote:
> On Tue, Oct 06, 2015 at 06:04:50PM +0200, Peter Zijlstra wrote:
> > On Mon, Sep 21, 2015 at 07:46:11PM +0200, Oleg Nesterov wrote:
> > > On 09/18, Peter Zijlstra wrote:
> > > >
> > > > the text is correct, right?
> > >
> > > Yes, it
On Tue, Oct 06, 2015 at 02:12:31PM -0700, Yang Shi wrote:
> When running kprobe test on arm64 rt kernel, it reports the below warning:
>
> root@qemu7:~# modprobe kprobe_example
> BUG: sleeping function called from invalid context at
> kernel/locking/rtmutex.c:917
> in_atomic(): 0, irqs_disabled()
s a documentation aid.
Documentation/memory-barriers.txt is updated to describe more clearly
the ACQUIRE and RELEASE ordering in this area and to show an example of
the new barrier in action.
Cc: Boqun Feng
Cc: Paul E. McKenney
Cc: Peter Zijlstra
Signed-off-by: Will Deacon
---
v1 -> v2: - Cla
Hi again, Drew,
On Thu, Sep 24, 2015 at 06:52:57PM +0100, Will Deacon wrote:
> On Mon, Aug 17, 2015 at 10:40:36PM +0100, Drew Richardson wrote:
> > So my suggestion to solve the problem is that the kernel can have the
> > list of events as proposed in the patch.
>
> Sorry,
Hi Peter,
Thanks for the headache ;)
On Wed, Oct 07, 2015 at 01:19:15PM +0200, Peter Zijlstra wrote:
> On Wed, Oct 07, 2015 at 11:59:28AM +0100, Will Deacon wrote:
> > As much as we'd like to live in a world where RELEASE -> ACQUIRE is
> > always cheaply ordered and c
Now that the core code supports acquire/release/relaxed versions of
the atomic_inc family, implement only the _relaxed flavours in the ARM
backend so that we get all of the others for free.
Cc: Davidlohr Bueso
Cc: Peter Zijlstra
Cc: Thomas Gleixner
Signed-off-by: Will Deacon
---
This sits on
Hi Linus,
Please pull the following arm64 fixes for 4.3-rc5. They address a couple
of issues found with RT, a broken initrd message in the console log and
a simple performance fix for some MMC workloads. Headlines in the tag.
Thanks,
Will
--->8
The following changes since commit 049e6dde7e57f0
On Mon, Aug 31, 2015 at 01:20:31PM +0100, Marc Zyngier wrote:
> On Sun, 30 Aug 2015 21:15:56 +0800
> Hanjun Guo wrote:
> > I agree. In arch/arm64/kernel/irq.c the irq migrate code is the same
> > as ARM32, and it's duplicate. But this is a bugfix, can we fix it in
> > a simple way, and refactor th
Hi Peter,
On Wed, Aug 26, 2015 at 07:16:59PM +0100, Peter Zijlstra wrote:
> I tried to keep this email short, but failed miserably at this. For
> the TL;DR skip to the tail.
[...]
> There are a few options:
>
> 1) punt, mandate they're both fully ordered and stop thinking about it
>
> 2) mak
On Tue, Sep 01, 2015 at 05:42:47PM +0100, Peter Zijlstra wrote:
> On Tue, Sep 01, 2015 at 05:31:40PM +0100, Will Deacon wrote:
> > On Wed, Aug 26, 2015 at 07:16:59PM +0100, Peter Zijlstra wrote:
> > > I tried to keep this email short, but failed miserably at this. For
> >
On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote:
> On Fri, Aug 28, 2015 at 10:16:02PM +0800, Boqun Feng wrote:
> > Ah.. just read through the thread you mentioned, I might misunderstand
> > you, probably because I didn't understand RCpc well..
> >
> > You are saying that in a RELEAS
On Sat, Oct 10, 2015 at 12:39:25PM -0500, Timur Tabi wrote:
> On Tue, Sep 22, 2015 at 12:59 PM, Robert Richter wrote:
> >
> > -#define L1_CACHE_SHIFT 6
> > +#define L1_CACHE_SHIFT 7
> > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
>
> Would it be better if this were a Kco
On Mon, Oct 12, 2015 at 09:17:50AM +0800, Boqun Feng wrote:
> On Thu, Oct 01, 2015 at 11:03:01AM -0700, Paul E. McKenney wrote:
> > On Thu, Oct 01, 2015 at 07:13:04PM +0200, Peter Zijlstra wrote:
> > > On Thu, Oct 01, 2015 at 08:09:09AM -0700, Paul E. McKenney wrote:
> > > > On Thu, Oct 01, 2015 at
On Wed, Sep 16, 2015 at 04:49:29PM +0100, Boqun Feng wrote:
> Some atomic operations now have _{relaxed, acquire, release} variants,
> this patch then adds some trivial tests for two purpose:
>
> 1.test the behavior of these new operations in single-CPU
> environment.
> 2.make their
On Fri, Oct 09, 2015 at 09:53:32AM -0700, Drew Richardson wrote:
> On Fri, Oct 09, 2015 at 11:13:38AM +0100, Will Deacon wrote:
> > On Wed, Oct 07, 2015 at 11:28:18AM -0700, Drew Richardson wrote:
> > > diff --git a/arch/arm/kernel/perf_event_v7.c
> > > b/arch
On Tue, Oct 13, 2015 at 01:10:48PM +1100, Stephen Rothwell wrote:
> Today's linux-next merge of the tip tree got a conflict in:
>
> arch/arm64/include/asm/atomic.h
>
> between commit:
>
> 305d454aaa29 ("arm64: atomics: implement native {relaxed, acquire, release}
> atomics")
>
> from the a
On Mon, Oct 12, 2015 at 10:14:04PM +0800, Boqun Feng wrote:
> On powerpc, acquire and release semantics can be achieved with
> lightweight barriers("lwsync" and "ctrl+isync"), which can be used to
> implement __atomic_op_{acquire,release}.
>
> For release semantics, since we only need to ensure al
On Mon, Oct 12, 2015 at 10:14:06PM +0800, Boqun Feng wrote:
> Implement cmpxchg{,64}_relaxed and atomic{,64}_cmpxchg_relaxed, based on
> which _release variants can be built.
>
> To avoid superfluous barriers in _acquire variants, we implement these
> operations with assembly code rather use __ato
On Mon, Oct 12, 2015 at 11:10:38AM -0700, Drew Richardson wrote:
> On Mon, Oct 12, 2015 at 03:30:25PM +0100, Will Deacon wrote:
> > I think this looks much better, thanks. The only thing left to do is
> > re-use some of the existing event descriptions from the enum
> > arm
On Tue, Oct 13, 2015 at 03:10:55PM +0100, Catalin Marinas wrote:
> On Mon, Oct 12, 2015 at 10:28:18AM +0800, yalin wang wrote:
> > Add ioremap_cache macro, because some code will test if this macro
> > is defined or not, and will generate a generric version if not defined,
> > for example, memremap
On Tue, Oct 13, 2015 at 10:32:59PM +0800, Boqun Feng wrote:
> On Tue, Oct 13, 2015 at 02:24:04PM +0100, Will Deacon wrote:
> > On Mon, Oct 12, 2015 at 10:14:06PM +0800, Boqun Feng wrote:
> > > Implement cmpxchg{,64}_relaxed and atomic{,64}_cmpxchg_relaxed, based on
> > &
On Tue, Oct 13, 2015 at 10:58:30PM +0800, Boqun Feng wrote:
> On Tue, Oct 13, 2015 at 03:43:33PM +0100, Will Deacon wrote:
> > Putting a barrier in the middle of that critical section is probably a
> > terrible idea, and that's why I thought you were avoiding it (hence my
>
On Tue, Oct 13, 2015 at 08:02:25PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 22, 2015 at 04:50:40PM -0400, Waiman Long wrote:
> > This patch replaces the cmpxchg() and xchg() calls in the native
> > qspinlock code with more relaxed versions of those calls to enable
> > other architectures to adopt
On Wed, Oct 14, 2015 at 09:47:35AM +0800, Boqun Feng wrote:
> On Tue, Oct 13, 2015 at 04:04:27PM +0100, Will Deacon wrote:
> > On Tue, Oct 13, 2015 at 10:58:30PM +0800, Boqun Feng wrote:
> > > On Tue, Oct 13, 2015 at 03:43:33PM +0100, Will Deacon wrote:
> > > > Putt
- prop = of_get_property(of_chosen, "linux,pci-probe-only", NULL);
> - if (prop) {
> - if (*prop)
> - pci_add_flags(PCI_PROBE_ONLY);
> - else
> - pci_clear_flags(PCI_PROBE_ONLY);
> - }
> + of_pci_chec
On Sat, Sep 05, 2015 at 06:53:02PM +0100, Peter Zijlstra wrote:
> On Wed, Sep 02, 2015 at 02:18:53PM -0700, Linus Torvalds wrote:
> > So I think we could possibly relax the requirements (and document this
> > very clearly) to say that the futex operation must be totally ordered
> > wrt any other _u
Dammit guys, it's never simple is it?
On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote:
> To that end, the herd tool can make a diagram of what it thought
> happened, and I have attached it. I used this diagram to try and force
> this scenario at https://www.cl.cam.ac.uk/~pes20/pp
On Thu, Oct 15, 2015 at 02:12:41PM +0200, Szabolcs Nagy wrote:
> * Will Deacon [2015-10-09 11:33:52 +0100]:
>
> > On Fri, Oct 09, 2015 at 03:59:40PM +0530, Manjeet Pawar wrote:
> > > MINSIGSTKSZ and SIGSTKSZ for ARM64 are not correctly set in latest kernel.
> > &g
On Thu, Oct 15, 2015 at 02:46:16PM +0200, Arnd Bergmann wrote:
> On Thursday 15 October 2015 20:12:35 Li Bin wrote:
> >
> > +#ifdef CONFIG_FUNCTION_GRAPH_TRACER
> > +static void print_ftrace_graph_addr(unsigned long addr,
> > + struct task_struct *tsk,
> > +
On Thu, Oct 15, 2015 at 10:17:47AM +0100, Vladimir Murzin wrote:
> We might need the same change for arm64 counterpart (see
> arch/arm64/kernel/armv8_deprecated.c).
Something like below?
Will
>From 63c3e83073cfac2e011adf0ed6f335275cc977a7 Mon Sep 17 00:00:00 2001
From: Will Deacon
On Tue, Oct 13, 2015 at 08:36:45AM -0700, Drew Richardson wrote:
> Add additional information about the ARM architected hardware events
> to make counters self describing. This makes the hardware PMUs easier
> to use as perf list contains possible events instead of users having
> to refer to docume
TKSZ and SIGSTKSZ to match glibc
- Wire up some new compat syscalls
Manjeet Pawar (1):
arm64: Fix MINSIGSTKSZ and SIGSTKSZ
Will Deacon (2):
arm64: errata: use KBUILD_CFLAGS_MODULE for erratum #843419
arm64: compat: wir
On Thu, Oct 15, 2015 at 11:35:10AM +0100, Will Deacon wrote:
> Dammit guys, it's never simple is it?
I re-read this and it's even more confusing than I first thought.
> On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote:
> > To that end, the herd tool can mak
On Thu, Oct 15, 2015 at 08:15:06AM -0700, Drew Richardson wrote:
> On Thu, Oct 15, 2015 at 02:21:12PM +0100, Will Deacon wrote:
> > On Tue, Oct 13, 2015 at 08:36:45AM -0700, Drew Richardson wrote:
> > > Add additional information about the ARM architected hardware events
>
On Wed, Oct 14, 2015 at 02:54:19PM +0200, Joerg Roedel wrote:
> On Fri, Oct 09, 2015 at 10:23:05AM +0800, Yong Wu wrote:
> > This patch is for ARM Short Descriptor Format.
> >
> > Signed-off-by: Yong Wu
>
> I think it would be good if Will Deacon could have a l
On Thu, Oct 15, 2015 at 01:21:54PM +, Jungseok Lee wrote:
> dump_backtrace() has its own backtrace logic unlike perf callchain which
> relies on walk_stackframe(). They behave differently when a symbol is
> recorded. Perf writes it down *before* calling unwind_frame(), but
> dump_backtrace() pr
Hi Paul,
On Tue, Sep 01, 2015 at 10:45:40PM +0100, Paul E. McKenney wrote:
> On Tue, Sep 01, 2015 at 08:00:27PM +0100, Will Deacon wrote:
> > On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote:
> > > Yes, the difference between RCpc and RCsc is in the
y it out: fetch linux-next/akpm,
> apply this patch, build/run a membarrier-enabled kernel, and do make
> kselftest. ]
>
> Signed-off-by: Mathieu Desnoyers
> CC: Andrew Morton
> CC: linux-...@vger.kernel.org
> CC: Catalin Marinas
> CC: Will Deacon
> ---
> arch/
On Wed, Aug 26, 2015 at 04:10:34PM +0100, Chris Metcalf wrote:
> On 08/26/2015 06:36 AM, Will Deacon wrote:
> > On Tue, Aug 25, 2015 at 08:55:52PM +0100, Chris Metcalf wrote:
> >> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
> >> index d882b8
On Sun, Aug 30, 2015 at 07:19:59AM +0100, yalin wang wrote:
> This patch add kc_offset_to_vaddr() and kc_vaddr_to_offset(),
> the default version doesn't work on arm64, because arm64 kernel address
> is below the PAGE_OFFSET, like module address and vmemmap address are
> all below PAGE_OFFSET addre
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