This patch adds NAND DT properties for NS2 SVK to configure the bus
width width and OOB sector size
Signed-off-by: Prafulla Kota
Signed-off-by: Ray Jui
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
b
This patch adds big endian and ONFI support for various iProc based
SoCs that use the core brcmstb NAND controller
This patch was originally implemented by Prafulla Kota
and fully tested on iProc based NS2 SVK
Signed-off-by: Prafulla Kota
Signed-off-by: Ray Jui
---
drivers/mtd/nand/brcmnand
branch: iproc-nand-be-v2
Changes from v1:
- Fixed minor format by adding braces around the 'else'
Ray Jui (2):
mtd: brcmnand: iProc big endian and ONFI support
arm64: dts: Updated NAND DT properties for NS2 SVK
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 2 ++
drivers/mtd/nan
:
'pinconf_generic_dt_node_to_map_group' undeclared here (not in a function)
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
Signed-off-by: Randy Dunlap
Cc: Ray Jui
Cc: bcm-kernel-feedback-l...@broadcom.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
---
drive
Hi Daniel,
On 6/16/2016 2:26 PM, Daniel Lezcano wrote:
The init functions do not return any error. They behave as the following:
- panic, thus leading to a kernel crash while another timer may work and
make the system boot up correctly
or
- print an error and let the caller unawa
(bcm_kona, "bcm,kona-timer", kona_timer_init);
+CLOCKSOURCE_OF_DECLARE_RET(bcm_kona, "bcm,kona-timer", kona_timer_init);
Looks good to me!
Acked-by: Ray Jui
Thanks,
Ray
Hi Rafal,
On 7/29/2016 5:58 AM, Rafał Miłecki wrote:
From: Rafał Miłecki
This clock is present on cheaper Northstar devices like BCM53573 or
BCM47189 using Corex-A7. This driver uses PMU (Power Management Unit)
to calculate clock rate and allows using it in a generic (clk_*) way.
I thought
On 7/29/2016 1:46 PM, Rafał Miłecki wrote:
On 29 July 2016 at 22:44, Ray Jui wrote:
On 7/29/2016 5:58 AM, Rafał Miłecki wrote:
From: Rafał Miłecki
This clock is present on cheaper Northstar devices like BCM53573 or
BCM47189 using Corex-A7. This driver uses PMU (Power Management Unit)
to
On 7/29/2016 1:55 PM, Florian Fainelli wrote:
On 07/29/2016 01:52 PM, Rafał Miłecki wrote:
On 29 July 2016 at 22:49, Ray Jui wrote:
On 7/29/2016 1:46 PM, Rafał Miłecki wrote:
On 29 July 2016 at 22:44, Ray Jui wrote:
On 7/29/2016 5:58 AM, Rafał Miłecki wrote:
From: Rafał Miłecki
Hi Bjorn,
On 8/30/2016 10:04 AM, Ray Jui wrote:
On 8/30/2016 10:00 AM, Bjorn Helgaas wrote:
On Tue, Aug 30, 2016 at 09:36:52AM -0700, Ray Jui wrote:
On 8/30/2016 6:37 AM, Bjorn Helgaas wrote:
On Mon, Aug 29, 2016 at 05:37:09PM -0700, Ray Jui wrote:
Hi Bjorn,
On 8/24/2016 10:54 AM
Hi All,
I'm writing to check with you to see if the latest arm-smmu.c driver in
v4.12-rc Linux for smmu-500 can support mapping that is only specific to
a particular physical address range while leave the rest still to be
handled by the client device. I believe this can already be supported by
the
Hi Will,
On 5/30/17 8:14 AM, Will Deacon wrote:
> On Mon, May 29, 2017 at 06:18:45PM -0700, Ray Jui wrote:
>> I'm writing to check with you to see if the latest arm-smmu.c driver in
>> v4.12-rc Linux for smmu-500 can support mapping that is only specific to
>> a particu
Hi Srinath and Scott,
On 5/30/17 8:44 AM, Scott Branden wrote:
> Hi Srinath,
>
>
> On 17-05-30 02:08 AM, Srinath Mannam wrote:
>> We found a concurrency issue in NVMe Init when we initialize
>> multiple NVMe connected over PCIe switch.
>>
>> Setup details:
>> - SMP system with 8 ARMv8 cores ru
Hi Marc,
On 5/30/17 9:59 AM, Marc Zyngier wrote:
> On 30/05/17 17:49, Ray Jui wrote:
>> Hi Will,
>>
>> On 5/30/17 8:14 AM, Will Deacon wrote:
>>> On Mon, May 29, 2017 at 06:18:45PM -0700, Ray Jui wrote:
>>>> I'm writing to check with you to see i
On 5/30/17 11:10 AM, Scott Branden wrote:
> Hi Ray,
>
>
> On 17-05-30 10:04 AM, Ray Jui wrote:
>> Hi Srinath and Scott,
>>
>> On 5/30/17 8:44 AM, Scott Branden wrote:
>>> Hi Srinath,
>>>
>>>
>>> On 17-05-30 02:08 AM, Srinath Ma
Hi Kishon,
On 10/6/2015 7:25 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 21 September 2015 10:47 PM, Ray Jui wrote:
>> This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
>> on Cygnus
>>
>> Signed-off-by: Ray Jui
>> Reviewe
On 10/6/2015 12:20 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 06 October 2015 10:43 PM, Ray Jui wrote:
>> Hi Kishon,
>>
>> On 10/6/2015 7:25 AM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Monday 21 September 2015 10:4
On 8/28/2015 4:47 PM, Jon Mason wrote:
> Add a very minimalistic set of Northstar Plus Device Tree files which
> describes the SoC and the BCM958625 implementation. The perpherials
> described are:
>
> ARM Cortex A9 CPU
> 2 8250 UARTs
> ARM GIC
> PL310 L2 Cache
> ARM A9 Global timer
>
> Signed
On 8/30/2015 7:24 PM, Jon Mason wrote:
> On Fri, Aug 28, 2015 at 05:20:20PM -0700, Ray Jui wrote:
>>
>>
>> On 8/28/2015 4:47 PM, Jon Mason wrote:
>>> Add a very minimalistic set of Northstar Plus Device Tree files which
>>> describes the SoC and the BCM
BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D
x27;d like to cross check with you and make sure the way how I
partition these drivers are acceptable.
Thanks,
Ray
On 5/21/2015 6:07 PM, Ray Jui wrote:
> This patch series adds support for the Cygnus PCIe PHY and support of the
> MDC/MDIO bus interface found in various iProc based of SoCs. The
On 10/13/2015 1:06 PM, Hauke Mehrtens wrote:
> On 10/13/2015 10:02 PM, Arnd Bergmann wrote:
>> The iproc PCI driver tries to figure out whether the MMIO window has
>> a valid size, but does this using a 64-bit modulo operation, which
>> is not allowed on 32-bit kernels and leads to a link error:
Shouldn't the device tree binding document go with the other patch
series since both the binding document and drivers are merged by Michael
or Stephen?
On 10/13/2015 2:22 PM, Jon Mason wrote:
> Document the device tree bindings for Broadcom Northstar Plus
> architecture based clock controller
>
>
Same as this patch. I thought device tree binding document should go
with the clock driver changes.
Strictly speaking, device tree binding document should always go before
the driver changes. In the binding document the DT interface is defined,
then changes are implemented in the driver.
Ray
On
On 10/13/2015 2:38 PM, Jon Mason wrote:
> On Sat, Oct 10, 2015 at 04:39:00PM +0200, Hauke Mehrtens wrote:
>> On 10/03/2015 12:22 AM, Jon Mason wrote:
>>> Add device tree files for Broadcom Northstar based SVKs. Since the
>>> bcm5301x.dtsi already exists, all that is necessary is the dts files to
On 10/14/2015 8:44 AM, Jon Mason wrote:
> On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote:
>> Same as this patch. I thought device tree binding document should go
>> with the clock driver changes.
>>
>> Strictly speaking, device tree binding document should alw
On 10/15/2015 9:00 AM, Bjorn Helgaas wrote:
> On Tue, Oct 13, 2015 at 11:00:31PM +0200, Arnd Bergmann wrote:
>> On Tuesday 13 October 2015 13:11:34 Ray Jui wrote:
>>>>> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
>>>>>
On 10/15/2015 1:40 PM, Scott Branden wrote:
> We need some sort of kconfig option to differentiate NS2 clock driver
> from being pulled in all the time.
>
> On 15-10-15 12:48 PM, Jon Mason wrote:
>> The Broadcom Northstar 2 SoC is architected under the iProc
>> architecture. It has the following
On 10/15/2015 2:10 PM, Jon Mason wrote:
> On Thu, Oct 15, 2015 at 02:04:09PM -0700, Scott Branden wrote:
>> Hi Ray,
>>
>> Comment at near end.
>>
>> On 15-10-15 01:55 PM, Ray Jui wrote:
>>>
>>>
>>> On 10/15/2015 1:40 PM, Scot
This will
> avoid pointer type-cast issues on both 32bit and 64bit systems.
>
> This patch fixes pointer type-cast issue in brcmnand_write()
> as-per above info.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Vikram Prakash
> Reviewed-by: Ray Jui
> Reviewed-by: Scott B
-by: Anup Patel
> Reviewed-by: Vikram Prakash
> Reviewed-by: Ray Jui
> Reviewed-by: Pramod KUMAR
> Reviewed-by: Scott Branden
> ---
> drivers/mtd/nand/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers
e going to change it
to Broadcom Limited, :)
Thanks for fixing this!
Acked-by: Ray Jui
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Please read the FAQ at http://www.tux.org/lkml/
This patch fixes incorrect iProc PLL clock frequency calculation. The issue
is exposed when Cygnus audio PLL was being added.
This patch is based on v4.3-rc5 and has been tested on Cygnus bcm958305k
wirelss audio board
This full tree is available here:
repo: https://github.com/Broadcom/cygnus-lin
ff-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/clk/bcm/clk-iproc-pll.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 2dda4e8..d679ab8 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
ff-by: Pramod Kumar
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
b/Documentation/devicetree/bindings/pi
On 15-10-19 02:49 PM, Stephen Boyd wrote:
On 10/16, Ray Jui wrote:
From: Simran Rai
This patch affects the clocks that use fractional ndivider in their
PLL output frequency calculation. Instead of 2^20 divide factor, the
clock's ndiv integer shift was used. Fixed the bug by replacing
This patch fixes incorrect iProc PLL clock frequency calculation. The issue
is exposed when Cygnus audio PLL was being added.
This patch is based on v4.3-rc5 and has been tested on Cygnus bcm958305k
wirelss audio board
This full tree is available here:
repo: https://github.com/Broadcom/cygnus-lin
ff-by: Ray Jui
Reviewed-by: Scott Branden
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
---
drivers/clk/bcm/clk-iproc-pll.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-ip
On 10/23/2015 6:02 AM, Laurent Pinchart wrote:
Hi Rob,
On Friday 23 October 2015 06:51:28 Rob Herring wrote:
On Fri, Oct 23, 2015 at 4:08 AM, Laurent Pinchart wrote:
On Thursday 22 October 2015 18:41:05 Rob Herring wrote:
On Thu, Oct 22, 2015 at 1:52 PM, Ray Jui wrote:
On 10/22/2015 11:43
Hi Pramod,
On 10/26/2015 10:08 AM, Pramod Kumar wrote:
-Original Message-
From: Ray Jui [mailto:r...@broadcom.com]
Sent: 23 October 2015 21:38
To: Laurent Pinchart; Rob Herring
Cc: Pramod Kumar; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Scott
Branden; Russell King; Linus
Hi Jisheng,
On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
Inspired by Russell King's patch[1], I found current iproc also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were
Hi Pramod,
On 10/26/2015 11:06 AM, Pramod Kumar wrote:
Hi Ray,
-Original Message-
From: Ray Jui [mailto:r...@broadcom.com]
Sent: 26 October 2015 22:43
To: Pramod Kumar; Laurent Pinchart; Rob Herring
Cc: Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Scott Branden; Russell
King
Hi Arnd,
On 10/1/2015 2:52 AM, Arnd Bergmann wrote:
> On Thursday 01 October 2015 14:29:21 Bharat Kumar Gogada wrote:
>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>
>> Signed-off-by: Bharat Kumar Gogada
>> Signed-off-by: Ravi Kiran Gummaluri
>> ---
>> Removed unneccessary comm
On 10/2/2015 3:36 PM, Arnd Bergmann wrote:
> On Thursday 01 October 2015 17:44:36 Ray Jui wrote:
>>
>> Sorry for stealing this discussion, :)
>>
>> I have some questions here, since this affects how I should implement
>> the MSI support for iProc based PCIe
Hi Lorenzo/Bjorn,
Could you please help to review this patch series when you have time?
I believe I have addressed major comment in v1 from Bjorn and answered
all questions from Lorenzo.
Thanks,
Ray
On 6/11/2018 5:21 PM, Ray Jui wrote:
This patch series improves the Broadcom PAXC support
Hi Guenter/Rob,
Kindly let me know how you want to proceed with this?
Thanks,
Ray
On 6/6/2018 4:39 PM, Ray Jui wrote:
On 6/6/2018 9:33 AM, Rob Herring wrote:
On Wed, Jun 6, 2018 at 11:19 AM, Guenter Roeck
wrote:
On 06/05/2018 12:41 PM, Rob Herring wrote:
On Mon, May 28, 2018 at 11:01
-rc1
Ray Jui (2):
dt-bindings: phy: Add binding doc for Stingray PCIe PHY
phy: bcm-sr-pcie: Add Stingray PCIe PHY driver
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 39 +++
drivers/phy/broadcom/Kconfig | 10 +
drivers/phy/broadcom/Makefile
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex
Signed-off-by: Ray Jui
---
drivers/phy/broadcom/Kconfig | 10 ++
drivers/phy/broadcom/Makefile | 2 +
drivers/phy/broadcom/phy-bcm-sr-pcie.c | 306 +
3 files changed, 318
Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based
root complex
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation
Hi Lorenzo,
On 6/21/2018 9:48 AM, Lorenzo Pieralisi wrote:
On Wed, Jun 20, 2018 at 10:26:28AM -0700, Ray Jui wrote:
Hi Lorenzo/Bjorn,
Could you please help to review this patch series when you have time?
I believe I have addressed major comment in v1 from Bjorn and answered all
questions
ra Bhivare
Signed-off-by: Ray Jui
Reviewed-by: Andy Gospodarek
---
drivers/pci/controller/pcie-iproc.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c
b/drivers/pci/controller/pcie-iproc.c
index 3160e9342a2f..c20fd6bd68fd 100644
--- a/drivers/pci/contr
On 8/28/2018 10:54 AM, Florian Fainelli wrote:
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interf
On 7/26/2018 12:16 PM, Arun Parameswaran wrote:
On 18-07-26 12:06 PM, Andrew Lunn wrote:
On Thu, Jul 26, 2018 at 11:36:19AM -0700, Arun Parameswaran wrote:
Modify the register offsets in the Broadcom iProc mdio mux to start
from the top of the register address space.
Earlier the base addr
Hi Bjorn,
On 7/11/2018 6:11 AM, Bjorn Helgaas wrote:
On Mon, Jun 11, 2018 at 05:21:03PM -0700, Ray Jui wrote:
Activate PAXC bridge quirk for more PAXC based PCIe root complex with
the following PCIe device ID:
0xd750, 0xd802, 0xd804
Signed-off-by: Ray Jui
Because this quirk_paxc_bridge
Hi Lorenzo,
On 1/11/2018 9:15 AM, Lorenzo Pieralisi wrote:
On Tue, Jan 09, 2018 at 11:45:40AM -0800, Ray Jui wrote:
With the inbound DMA mapping supported added, the iProc PCIe driver
parses DT property "dma-ranges" through call to
"of_pci_dma_range_parser_init". In th
c-platform.c to only enable the
inbound DMA mapping logic when DT property "dma-ranges" is present
Fixes: dd9d4e7498de3 ("PCI: iproc: Add inbound DMA mapping support")
Reported-by: Rafał Miłecki
Signed-off-by: Ray Jui
Tested-by: Rafał Miłecki
cc: # 4.10+
---
dr
c-platform.c to only enable the
inbound DMA mapping logic when DT property "dma-ranges" is present
fixes: dd9d4e7498de3 ("PCI: iproc: Add inbound DMA mapping support")
Reported-by: Rafał Miłecki
Signed-off-by: Ray Jui
Tested-by: Rafał Miłecki
Cc: # 4.10+
---
drivers/pci/hos
Hi Lorenzo,
On 7/9/2018 10:22 AM, Lorenzo Pieralisi wrote:
On Mon, Jun 11, 2018 at 05:21:02PM -0700, Ray Jui wrote:
This patch series improves the Broadcom PAXC support by 1) adding more
quirks for specific versions of PAXC controllers; 2) adding logic to
reject internally unconfigured
06-12 05:51, Ray Jui wrote:
Activate PAXC bridge quirk for more PAXC based PCIe root complex with
the following PCIe device ID:
0xd750, 0xd802, 0xd804
Signed-off-by: Ray Jui
---
drivers/pci/quirks.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
in
Add PAXC support to Broadcom Stingray SoC
Signed-off-by: Ray Jui
Signed-off-by: Peter Spreadborough
---
.../boot/dts/broadcom/stingray/stingray-pcie.dtsi | 54 ++
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 11 +
2 files changed, 65 insertions(+)
create mode
From: Vladimir Olovyannikov
Add bcm958802a802x dts to be used on all Stingray smart NIC PS225 board
variants
Signed-off-by: Vladimir Olovyannikov
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
arch/arm64/boot/dts/broadcom/stingray/Makefile | 2 ++
.../boot/dts/broadcom/stingray
This patch series adds DT support for Stingray smart NIC boards
This patch series is based off v4.18-rc3 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sr-smartnic-dt-v1
Ray Jui (1):
arm64: dts: stingray: add PAXC support
Vladimir Olovyannikov (1
On 6/27/2018 11:33 AM, Guenter Roeck wrote:
On Wed, Jun 20, 2018 at 10:39:16AM -0700, Ray Jui wrote:
Hi Guenter/Rob,
Kindly let me know how you want to proceed with this?
If I recall correctly, the patch series does not add a new problem
but merely exposes one. Is my recollection correct
On 6/27/2018 11:42 AM, Guenter Roeck wrote:
On Wed, Jun 27, 2018 at 11:38:48AM -0700, Ray Jui wrote:
On 6/27/2018 11:33 AM, Guenter Roeck wrote:
On Wed, Jun 20, 2018 at 10:39:16AM -0700, Ray Jui wrote:
Hi Guenter/Rob,
Kindly let me know how you want to proceed with this?
If I recall
Hi Guenter/Florian,
On 6/27/2018 11:55 AM, Guenter Roeck wrote:
On Wed, Jun 27, 2018 at 11:47:21AM -0700, Ray Jui wrote:
On 6/27/2018 11:42 AM, Guenter Roeck wrote:
On Wed, Jun 27, 2018 at 11:38:48AM -0700, Ray Jui wrote:
On 6/27/2018 11:33 AM, Guenter Roeck wrote:
On Wed, Jun 20, 2018
On 5/24/2018 9:19 AM, Guenter Roeck wrote:
On Wed, May 23, 2018 at 05:15:22PM -0700, Ray Jui wrote:
If the watchdog hardware is already enabled during the boot process,
when the Linux watchdog driver loads, it should reset the watchdog and
tell the watchdog framework. As a result, ping can be
On 5/24/2018 9:16 AM, Guenter Roeck wrote:
On Wed, May 23, 2018 at 05:15:20PM -0700, Ray Jui wrote:
Update the SP805 binding document to add optional 'timeout-sec'
devicetree property
Signed-off-by: Ray Jui
---
Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 +
This patch series updates Broadcom Stingray clock entries so they match the
latest ASIC datasheet
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sr-clk-v1
Ray Jui (3):
dt-bindings: clk: Update Stingray binding doc
Update clock output names in the Stingray clock DT nodes so they match
the binding document and the latest ASIC datasheet. Also add entries
for LCPLL2
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
.../boot/dts/broadcom/stingray/stingray-clock.dtsi | 26 --
1 file
Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
.../bindings/clock
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
drivers/clk/bcm/clk-sr.c | 135 -
include/dt-bindings/clock/bcm-sr.h | 24
Hi Clément,
Correct me if I'm wrong, but I thought the trend is to move to use
earlycon that can be activated from kernel command line for early print
before the serial driver is loaded.
Have you tried earlcon?
Thanks,
Ray
On 5/30/2018 6:19 AM, Clément Péron wrote:
From: Clément Peron
B
Hi Andy,
On 5/29/2018 5:59 PM, Andy Shevchenko wrote:
On Wed, May 30, 2018 at 12:58 AM, Ray Jui wrote:
Add PCIe legacy interrupt INTx support to the iProc PCIe driver by
modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC,
INTD share the same interrupt line connected to the
Hi Bjorn,
On 5/30/2018 10:27 AM, Bjorn Helgaas wrote:
On Thu, May 17, 2018 at 10:21:31AM -0700, Ray Jui wrote:
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
prevents the Linux PCIe stack from traversing the
Hi Stephen,
On 5/30/2018 4:41 PM, Stephen Boyd wrote:
Subject is missing an 's' on stringray?
Yes, will fix this.
Quoting Ray Jui (2018-05-25 09:45:16)
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Sig
This patch series updates Broadcom Stingray clock entries so they match the
latest ASIC datasheet
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sr-clk-v2
Changes since v1:
- Fix patch author to Pramod Kumar on all 3
From: Pramod Kumar
Update clock output names in the Stingray clock DT nodes so they match
the binding document and the latest ASIC datasheet. Also add entries
for LCPLL2
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
.../boot/dts/broadcom/stingray/stingray-clock.dtsi | 26
From: Pramod Kumar
Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
From: Pramod Kumar
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
drivers/clk/bcm/clk-sr.c | 135 -
include/dt-bindings
On 5/31/2018 1:22 AM, Clément Péron wrote:
Hi Rai,
On Wed, 30 May 2018 at 19:25, Ray Jui wrote:
Hi Clément,
Correct me if I'm wrong, but I thought the trend is to move to use
earlycon that can be activated from kernel command line for early print
before the serial driver is loaded.
Sorry Florian, I had a couple issues with my email client yesterday and
I'm not sure if you have received my reply.
Please see my reply inline.
On 5/31/2018 3:16 PM, Florian Fainelli wrote:
On 05/31/2018 10:24 AM, Ray Jui wrote:
On 5/31/2018 1:22 AM, Clément Péron wrote:
Hi Rai,
O
Hi Rob,
On 5/31/2018 9:25 AM, Rob Herring wrote:
On Fri, May 25, 2018 at 09:45:16AM -0700, Ray Jui wrote:
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
drivers
On 6/1/2018 12:02 PM, Rob Herring wrote:
On Fri, Jun 1, 2018 at 12:56 PM, Ray Jui wrote:
Hi Rob,
On 5/31/2018 9:25 AM, Rob Herring wrote:
On Fri, May 25, 2018 at 09:45:16AM -0700, Ray Jui wrote:
Update and add Stingray clock definitions and tables so they match the
binding document and
This patch series updates Broadcom Stingray clock entries so they match the
latest ASIC datasheet
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sr-clk-v3
Changes since v2:
- Move dt-binding header change to the same
From: Pramod Kumar
Update clock output names in the Stingray clock DT nodes so they match
the binding document and the latest ASIC datasheet. Also add entries
for LCPLL2
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
.../boot/dts/broadcom/stingray/stingray-clock.dtsi | 26
From: Pramod Kumar
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
---
drivers/clk/bcm/clk-sr.c | 135 +--
1 file changed, 120
From: Pramod Kumar
Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar
Signed-off-by: Ray Jui
Hi Lorenzo,
A friendly reminder: Have you had a chance to help to review the patch
series below?
Thanks,
Ray
On 6/21/2018 11:22 AM, Ray Jui wrote:
Hi Lorenzo,
On 6/21/2018 9:48 AM, Lorenzo Pieralisi wrote:
On Wed, Jun 20, 2018 at 10:26:28AM -0700, Ray Jui wrote:
Hi Lorenzo/Bjorn,
Could
Hi Lorenzo,
On 7/4/2018 8:13 AM, Lorenzo Pieralisi wrote:
On Tue, May 22, 2018 at 09:48:55AM -0700, Ray Jui wrote:
Hi Robin/Lorenzo,
On 5/21/2018 7:26 AM, Robin Murphy wrote:
On 21/05/18 14:33, Lorenzo Pieralisi wrote:
[+Robin]
On Fri, May 18, 2018 at 12:48:28PM -0700, Ray Jui wrote:
Hi
the driver so it can access the PCIe SS PHY block
- Rebase to v4.18-rc3
Changes since v1:
- Rebase from v4.17-rc5 to v4.18-rc1
Ray Jui (2):
dt-bindings: phy: Add binding doc for Stingray PCIe PHY
phy: bcm-sr-pcie: Add Stingray PCIe PHY driver
.../devicetree/bindings/phy/brcm,sr-pcie-phy.t
Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based
root complex
Signed-off-by: Ray Jui
---
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,sr
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex
Signed-off-by: Ray Jui
---
drivers/phy/broadcom/Kconfig | 10 +
drivers/phy/broadcom/Makefile | 2 +
drivers/phy/broadcom/phy-bcm-sr-pcie.c | 327 +
3 files changed, 339
Hi Kishon,
On 7/5/2018 4:39 AM, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 04 July 2018 11:52 PM, Ray Jui wrote:
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex
Signed-off-by: Ray Jui
---
drivers/phy/broadcom/Kconfig | 10 +
drivers/phy/broadcom/Makefile
Hi Lorenzo,
On 7/6/2018 9:20 AM, Lorenzo Pieralisi wrote:
On Mon, Jun 11, 2018 at 05:21:02PM -0700, Ray Jui wrote:
This patch series improves the Broadcom PAXC support by 1) adding more
quirks for specific versions of PAXC controllers; 2) adding logic to
reject internally unconfigured physical
On 7/5/2018 4:34 PM, Rob Herring wrote:
On Wed, Jul 04, 2018 at 11:22:12AM -0700, Ray Jui wrote:
Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based
root complex
Signed-off-by: Ray Jui
---
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 41
Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based
root complex
Signed-off-by: Ray Jui
Reviewed-by: Rob Herring
---
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex
Signed-off-by: Ray Jui
---
drivers/phy/broadcom/Kconfig | 10 ++
drivers/phy/broadcom/Makefile | 2 +
drivers/phy/broadcom/phy-bcm-sr-pcie.c | 305 +
3 files changed, 317
.17-rc5 to v4.18-rc1
Ray Jui (2):
dt-bindings: phy: Add binding doc for Stingray PCIe PHY
phy: bcm-sr-pcie: Add Stingray PCIe PHY driver
.../devicetree/bindings/phy/brcm,sr-pcie-phy.txt | 41 +++
drivers/phy/broadcom/Kconfig | 10 +
drivers/phy/broadco
On 6/12/2018 5:23 AM, p...@codeaurora.org wrote:
On 2018-06-12 13:57, p...@codeaurora.org wrote:
On 2018-06-12 05:51, Ray Jui wrote:
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
prevents the Linux PCIe
On 6/12/2018 1:29 AM, p...@codeaurora.org wrote:
On 2018-06-12 05:51, Ray Jui wrote:
The internal MSI parsing logic in certain revisions of PAXC root
complexes does not work properly and can casue corruptions on the
writes. They need to be disabled
Signed-off-by: Ray Jui
Reviewed-by: Scott
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