Hi Alex,
On Tue, Feb 25, 2025 at 10:07 PM Alexandre Ghiti wrote:
>
> On Tue, Feb 25, 2025 at 2:27 PM yunhui cui wrote:
> >
> > Hi Alex,
> >
> > On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti
> > wrote:
> > >
> > > Hi Yunhui,
Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones
Signed-off-by: Yunhui Cui
---
arch/riscv/kernel/cpufeature.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel
.
v5:
1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
v6:
Change hwprobe_ext0_has's second param to u64.
v7:
Rebase to the latest code of linux-next.
Yunhui Cui (3):
RISC-V: Enable cbo.clea
by: Samuel Holland
Signed-off-by: Yunhui Cui
---
tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +
1 file changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c
b/tools/testing/selftests/riscv/hwprobe/cbo.c
index a40541bb7c7d..5e
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Reviewed-by: Andrew Jones
Reviewed-by: Samuel Holland
Signed-off-by: Yunhui Cui
---
Documentation/arch/riscv/hwprobe.rst | 6 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include
Hi Alex,
On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti wrote:
>
> Hi Yunhui,
>
> On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui wrote:
> >
> > v1/v2:
> > There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode,
> > which mainly removes th
by: Samuel Holland
Signed-off-by: Yunhui Cui
---
tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +
1 file changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c
b/tools/testing/selftests/riscv/hwprobe/cbo.c
index a40541bb7c7d..5e
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Reviewed-by: Andrew Jones
Reviewed-by: Samuel Holland
Signed-off-by: Yunhui Cui
---
Documentation/arch/riscv/hwprobe.rst | 6 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include
Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones
Signed-off-by: Yunhui Cui
---
arch/riscv/kernel/cpufeature.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel
.
v5:
1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
v6:
Change hwprobe_ext0_has's second param to u64.
Yunhui Cui (3):
RISC-V: Enable cbo.clean/flush in usermode
RISC-V: hwprobe: Expose Zi
Hi drew,
On Tue, Jan 21, 2025 at 11:29 PM Andrew Jones wrote:
>
> On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui
&
Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones
Signed-off-by: Yunhui Cui
---
arch/riscv/kernel/cpufeature.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel
by: Samuel Holland
Signed-off-by: Yunhui Cui
---
tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +
1 file changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c
b/tools/testing/selftests/riscv/hwprobe/cbo.c
index a40541bb7c7d..5e
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Signed-off-by: Yunhui Cui
---
Documentation/arch/riscv/hwprobe.rst | 6 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_hwprobe.c
.
v5:
1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3):
RISC-V: Enable cbo.clean/flush in usermode
RISC-V: hwprobe: Expose Zicbom extension and its block size
RISC-V: selftests: A
Hi Samuel，
On Tue, Jan 14, 2025 at 1:28 PM Samuel Holland
wrote:
>
> Hi Yunhui,
>
> On 2025-01-13 8:19 PM, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui
&
Add test for Zicbom and its block size into CBO tests, when
Zicbom is present, test that cbo.clean/flush may be issued and works.
As the software can't verify the clean/flush functions, we just judged
that cbo.clean/flush isn't executed illegally.
Signed-off-by: Yunhui Cui
---
too
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Signed-off-by: Yunhui Cui
---
Documentation/arch/riscv/hwprobe.rst | 6 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_hwprobe.c
Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones
Signed-off-by: Yunhui Cui
---
arch/riscv/kernel/cpufeature.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel
.
Yunhui Cui (3):
RISC-V: Enable cbo.clean/flush in usermode
RISC-V: hwprobe: Expose Zicbom extension and its block size
RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst| 6 ++
arch/riscv/include/asm/hwprobe.h| 2 +-
arch/riscv
Hi drew,
On Mon, Jan 13, 2025 at 5:18 PM Andrew Jones wrote:
>
> On Mon, Jan 13, 2025 at 04:36:35PM +0800, Yunhui Cui wrote:
> > Add test for Zicbom and its block size into CBO tests, when
> > Zicbom is present, test that cbo.clean/flush may be issued and works.
> > As t
Hi drew,
On Mon, Jan 13, 2025 at 5:07 PM Andrew Jones wrote:
>
> On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui
> &g
Add test for Zicbom and its block size into CBO tests, when
Zicbom is present, test that cbo.clean/flush may be issued and works.
As the software can't verify the clean/flush functions, we just judged
that cbo.clean/flush isn't executed illegally.
Signed-off-by: Yunhui Cui
---
too
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Signed-off-by: Yunhui Cui
---
Documentation/arch/riscv/hwprobe.rst | 6 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_hwprobe.c
Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones
Signed-off-by: Yunhui Cui
---
arch/riscv/kernel/cpufeature.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel
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