Hi Samuel，
On Tue, Jan 14, 2025 at 1:28 PM Samuel Holland
<[email protected]> wrote:
>
> Hi Yunhui,
>
> On 2025-01-13 8:19 PM, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui <[email protected]>
> > ---
> > Documentation/arch/riscv/hwprobe.rst | 6 ++++++
> > arch/riscv/include/asm/hwprobe.h | 2 +-
> > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> > 4 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst
> > b/Documentation/arch/riscv/hwprobe.rst
> > index 955fbcd19ce9..0ea7754b2049 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -242,6 +242,9 @@ The following keys are defined:
> > * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
> > defined in version 1.0 of the RISC-V Pointer Masking extensions.
> >
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is
> > supported, as
> > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
> > riscv-CMOs.
> > +
> > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar
> > values to
> > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> > mistakenly classified as a bitmask rather than a value.
> > @@ -281,6 +284,9 @@ The following keys are defined:
> > * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value
> > describing the
> > performance of misaligned vector accesses on the selected set of
> > processors.
> >
> > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
> > + represents the size of the Zicbom block in bytes.
> > +
> > * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of
> > misaligned
> > vector accesses is unknown.
>
> The new key needs to go further down, below this list of possible values for
> the
> previous key.
I guess you mean to put it after
RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED, right?
>
> Regards,
> Samuel
>
> >
> > diff --git a/arch/riscv/include/asm/hwprobe.h
> > b/arch/riscv/include/asm/hwprobe.h
> > index 1ce1df6d0ff3..89379f9a2e6e 100644
> > --- a/arch/riscv/include/asm/hwprobe.h
> > +++ b/arch/riscv/include/asm/hwprobe.h
> > @@ -8,7 +8,7 @@
> >
> > #include <uapi/asm/hwprobe.h>
> >
> > -#define RISCV_HWPROBE_MAX_KEY 10
> > +#define RISCV_HWPROBE_MAX_KEY 11
> >
> > static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> > {
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h
> > b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 3af142b99f77..b15c0bd83ef2 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -73,6 +73,7 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> > #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
> > +#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50)
> > #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> > @@ -94,6 +95,7 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW 2
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_FAST 3
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4
> > +#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 11
> > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> >
> > /* Flags */
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c
> > b/arch/riscv/kernel/sys_hwprobe.c
> > index cb93adfffc48..04150e62f998 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -106,6 +106,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> > EXT_KEY(ZCA);
> > EXT_KEY(ZCB);
> > EXT_KEY(ZCMOP);
> > + EXT_KEY(ZICBOM);
> > EXT_KEY(ZICBOZ);
> > EXT_KEY(ZICOND);
> > EXT_KEY(ZIHINTNTL);
> > @@ -278,6 +279,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe
> > *pair,
> > if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
> > pair->value = riscv_cboz_block_size;
> > break;
> > + case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:
> > + pair->value = 0;
> > + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
> > + pair->value = riscv_cbom_block_size;
> > + break;
> > case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
> > pair->value = user_max_virt_addr();
> > break;
>
Thanks,
Yunhui
