On Tue, Jan 07, 2025 at 10:59:43PM +, Mark Brown wrote:
> The 2024 dpISA introduces a number of architecture features all of which
> only add new instructions so only require the addition of hwcaps and ID
> register visibility.
While working on SME fixes atop v6.14-rc1, I found this patch brea
On Wed, Jan 22, 2025 at 11:51:00AM +, Marc Zyngier wrote:
> On Fri, 17 Jan 2025 11:34:09 +0000, Mark Rutland wrote:
> > The TL;DR summary is that it's not sufficient for kvm_arch_vcpu_put_fp()
> > to fix up ZCR_ELx. Either:
> >
> > * That needs to be fixed u
On Fri, Dec 20, 2024 at 04:46:34PM +, Mark Brown wrote:
> The SVE portion of kvm_vcpu_put() is quite large, especially given the
> comments required. When we add similar handling for SME the function
> will get even larger, in order to keep things managable factor the SVE
> portion out of the
ss_save.
> * Remove unnecessary preempt_disable/enable and elaborate on comment why
> we want to disable interrupts and preemptions.
> * Use common struct kcsan_ctx in task_struct and for per-CPU interrupt
> contexts [Suggested by Mark Rutland].
This is generally looking good
On Thu, Oct 17, 2019 at 04:13:05PM +0200, Marco Elver wrote:
> This patch enables KCSAN for x86, with updates to build rules to not use
> KCSAN for several incompatible compilation units.
>
> Signed-off-by: Marco Elver
> ---
> v2:
> * Document build exceptions where no previous above comment expl
atomic_check_{read,write} [Suggested by Mark Rutland].
> ---
> include/asm-generic/atomic-instrumented.h | 393 +++---
> scripts/atomic/gen-atomic-instrumented.sh | 17 +-
> 2 files changed, 218 insertions(+), 192 deletions(-)
The script changes and generated code look fin
On Mon, Oct 21, 2019 at 02:40:31PM +0100, Steven Price wrote:
> On 18/10/2019 18:10, Mark Rutland wrote:
> > On Tue, Oct 15, 2019 at 06:56:51PM +0100, Mark Rutland wrote:
> [...]
> >>> +PV_TIME_ST
> >>> += ==
> >&g
On Tue, Oct 15, 2019 at 06:56:51PM +0100, Mark Rutland wrote:
> Hi Steven,
>
> On Fri, Oct 11, 2019 at 01:59:21PM +0100, Steven Price wrote:
> > Introduce a paravirtualization interface for KVM/arm64 based on the
> > "Arm Paravirtualized Time for Arm-Base Systems"
On Wed, Oct 16, 2019 at 10:39:52AM +0200, Marco Elver wrote:
> diff --git a/include/linux/sched.h b/include/linux/sched.h
> index 2c2e56bd8913..34a1d9310304 100644
> --- a/include/linux/sched.h
> +++ b/include/linux/sched.h
> @@ -1171,6 +1171,13 @@ struct task_struct {
> #ifdef CONFIG_KASAN
>
Hi Marco,
On Wed, Oct 16, 2019 at 10:39:58AM +0200, Marco Elver wrote:
> This adds KCSAN instrumentation to atomic-instrumented.h.
>
> Signed-off-by: Marco Elver
> ---
> include/asm-generic/atomic-instrumented.h | 192 +-
> scripts/atomic/gen-atomic-instrumented.sh | 9 +-
Hi Steven,
On Fri, Oct 11, 2019 at 01:59:21PM +0100, Steven Price wrote:
> Introduce a paravirtualization interface for KVM/arm64 based on the
> "Arm Paravirtualized Time for Arm-Base Systems" specification DEN 0057A.
I notice that as published, this is a BETA Draft, with the explicit
note:
| Th
On Tue, Aug 13, 2019 at 04:25:15PM +0530, Ganapatrao Kulkarni wrote:
> Hi Mark,
>
> On Mon, Aug 12, 2019 at 5:31 PM Mark Rutland wrote:
> >
> > On Tue, Jul 23, 2019 at 09:16:28AM +, Ganapatrao Kulkarni wrote:
> > > CCPI2 is a low-latency high-bandwidth s
On Tue, Jul 23, 2019 at 09:16:28AM +, Ganapatrao Kulkarni wrote:
> CCPI2 is a low-latency high-bandwidth serial interface for connecting
> ThunderX2 processors. This patch adds support to capture CCPI2 perf events.
It would be worth pointing out in the commit message how the CCPI2
counters dif
the feature lists accordingly, and remove the now redundant
rwsem-optimized list.
Signed-off-by: Mark Rutland
Cc: Jonathan Corbet
Cc: linux-doc@vger.kernel.org
---
.../locking/queued-rwlocks/arch-support.txt| 2 +-
.../locking/queued-spinlocks/arch-support.txt | 4 +--
.../locki
Hi,
Sorry for the (quite horrific) mangling my mailserver has inflicted via
my reply. Obviously, the confidentiality disclaimer is bogus, too.
I'll make sure I use the right SMTP server in future.
Mark.
On Wed, Jun 26, 2019 at 12:22:31PM +0000, Mark Rutland wrote:
> On Mon, May 20, 20
On Mon, May 20, 2019 at 03:27:17PM +, Gerald BAEZA wrote:
> The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC.
>
> This perf drivers supports the read, write, activate, idle and total
> time counters, described in the reference manual RM0436.
Is this document publicly access
On Thu, May 23, 2019 at 11:35:16AM -0700, Atish Patra wrote:
> Currently, last stage boot loaders such as U-Boot can accept only
> uImage which is an unnecessary additional step in automating boot flows.
>
> Add a PE/COFF compliant image header that boot loaders can parse and
> directly load kerne
for clarify and consistency.
> * Remove #ifdef, since it is assumed that if asm-generic bitops
> implementations are used, bitops-instrumented.h is not needed.
Thanks for sorting this out. FWIW:
Acked-by: Mark Rutland
Mark.
>
> Changes in v2:
> * Instrument word-sized access
> * Use sizeof(*bits).
Thatnks for cleaning these up! FWIW:
Acked-by: Mark Rutland
Mark.
>
> Changes in v2:
> * Use BITS_PER_LONG.
> * Use heap allocated memory for test, as newer compilers (correctly)
> warn on OOB stack
On Wed, May 29, 2019 at 04:15:01PM +0200, Marco Elver wrote:
> This adds a new header to asm-generic to allow optionally instrumenting
> architecture-specific asm implementations of bitops.
>
> This change includes the required change for x86 as reference and
> changes the kernel API doc to point
On Wed, May 29, 2019 at 04:14:59PM +0200, Marco Elver wrote:
> This adds bitops tests to the test_kasan module. In a follow-up patch,
> support for bitops instrumentation will be added.
>
> Signed-off-by: Marco Elver
> ---
> Changes in v2:
> * Use BITS_PER_LONG.
> * Use heap allocated memory for
On Wed, May 29, 2019 at 12:57:15PM +0200, Dmitry Vyukov wrote:
> On Wed, May 29, 2019 at 12:30 PM Peter Zijlstra wrote:
> >
> > On Wed, May 29, 2019 at 12:16:31PM +0200, Marco Elver wrote:
> > > On Wed, 29 May 2019 at 12:01, Peter Zijlstra wrote:
> > > >
> > > > On Wed, May 29, 2019 at 11:20:17AM
Hi,
On Tue, May 28, 2019 at 06:32:56PM +0200, Marco Elver wrote:
> +static noinline void __init kasan_bitops(void)
> +{
> + long bits = 0;
> + const long bit = sizeof(bits) * 8;
You can use BITS_PER_LONG here.
Thanks,
Mark.
On Tue, May 28, 2019 at 06:32:58PM +0200, Marco Elver wrote:
> This adds a new header to asm-generic to allow optionally instrumenting
> architecture-specific asm implementations of bitops.
>
> This change includes the required change for x86 as reference and
> changes the kernel API doc to point
On Sat, Jan 12, 2019 at 02:57:01PM +0800, Changbin Du wrote:
> This patch adds a new trace option 'funcgraph-retval' and is disabled by
> default. When this option is enabled, fgraph tracer will show the return
> value of each function. This is useful to find/analyze a original error
> source in a
On Mon, Nov 19, 2018 at 06:26:21PM +0100, Andrey Konovalov wrote:
> This commit splits the current CONFIG_KASAN config option into two:
> 1. CONFIG_KASAN_GENERIC, that enables the generic KASAN mode (the one
>that exists now);
> 2. CONFIG_KASAN_SW_TAGS, that enables the software tag-based KASAN
, which is necessary for sign_extend64().
With those fixed up, this patch looks sound to me:
Acked-by: Mark Rutland
Thanks,
Mark.
> +
> /*
> * Generic and tag-based KASAN require 1/8th and 1/16th of the kernel virtual
> * address space for the shadow region respectively. They c
On Mon, Nov 19, 2018 at 06:28:57PM +0100, Andrey Konovalov wrote:
> On Mon, Nov 19, 2018 at 6:26 PM, Andrey Konovalov
> wrote:
> > Changes in v11:
> > - Rebased onto 9ff01193 (4.20-rc3).
> > - Moved KASAN_SHADOW_SCALE_SHIFT definition to arch/arm64/Makefile.
> > - Added and used CC_HAS_KASAN_GENE
On Wed, Nov 14, 2018 at 09:06:23PM +0100, Andrey Konovalov wrote:
> On Tue, Nov 13, 2018 at 11:07 PM, Mark Rutland wrote:
> > On Tue, Nov 13, 2018 at 04:01:27PM +0100, Andrey Konovalov wrote:
> >> On Thu, Nov 8, 2018 at 1:22 PM, Mark Rutland wrote:
> >> > On Tue, No
On Tue, Nov 13, 2018 at 04:01:27PM +0100, Andrey Konovalov wrote:
> On Thu, Nov 8, 2018 at 1:22 PM, Mark Rutland wrote:
> > On Tue, Nov 06, 2018 at 06:30:27PM +0100, Andrey Konovalov wrote:
> >> show_pte in arm64 fault handling relies on the fact that the top byte of
> >&g
On Tue, Nov 06, 2018 at 06:30:27PM +0100, Andrey Konovalov wrote:
> show_pte in arm64 fault handling relies on the fact that the top byte of
> a kernel pointer is 0xff, which isn't always the case with tag-based
> KASAN.
That's for the TTBR1 check, right?
i.e. for the following to work:
On Tue, Nov 06, 2018 at 06:30:24PM +0100, Andrey Konovalov wrote:
> This commit adds a few helper functions, that are meant to be used to
> work with tags embedded in the top byte of kernel pointers: to set, to
> get or to reset (set to 0xff) the top byte.
>
> Reviewed-by: Andrey Ryabinin
> Revie
On Tue, Nov 06, 2018 at 06:30:22PM +0100, Andrey Konovalov wrote:
> A tag-based KASAN shadow memory cell contains a memory tag, that
> corresponds to the tag in the top byte of the pointer, that points to that
> memory. The native top byte value of kernel pointers is 0xff, so with
> tag-based KASAN
On Tue, Nov 06, 2018 at 06:30:20PM +0100, Andrey Konovalov wrote:
> This commit splits the current CONFIG_KASAN config option into two:
> 1. CONFIG_KASAN_GENERIC, that enables the generic KASAN mode (the one
>that exists now);
> 2. CONFIG_KASAN_SW_TAGS, that enables the software tag-based KASAN
Hi Andrey,
On Tue, Nov 06, 2018 at 06:30:21PM +0100, Andrey Konovalov wrote:
> Tag-based KASAN uses 1 shadow byte for 16 bytes of kernel memory, so it
> requires 1/16th of the kernel virtual address space for the shadow memory.
>
> This commit sets KASAN_SHADOW_SCALE_SHIFT to 4 when the tag-based
Hi Andrey,
On Tue, Nov 06, 2018 at 06:30:23PM +0100, Andrey Konovalov wrote:
> __kimg_to_phys (which is used by virt_to_phys) and _virt_addr_is_linear
> (which is used by virt_addr_valid) assume that the top byte of the address
> is 0xff, which isn't always the case with tag-based KASAN.
I'm conf
information through FDT.
>
> Signed-off-by: Peng Hao
Acked-by: Mark Rutland
Mark.
> ---
> drivers/misc/pvpanic.c | 66
> +++---
> 1 file changed, 63 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/misc/pvpanic.c b/dr
title fixed:
Acked-by: Mark Rutland
When sending DT bindings in future, please follow the process in:
Documentation/devicetree/bindings/submitting-patches.txt
... e.g., send the binding before the code using the binding.
Thanks,
Mark.
> ---
> .../devicetree/bindings/misc/p
On Thu, Nov 01, 2018 at 11:10:00PM +0800, Peng Hao wrote:
> On some architectures (e.g. arm64), it's preferable to use MMIO, since
> this can be used standalone. Add MMIO support to the pvpanic driver.
>
> Signed-off-by: Peng Hao
Acked-by: Mark Rutland
Mark.
> ---
>
e text.
>
> Signed-off-by: Peng Hao
Other than the commit title, this looks fine to me:
Acked-by: Mark Rutland
Mark.
> ---
> drivers/misc/pvpanic.c | 16 ++--
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/misc/pvpanic.c b/dri
On Thu, Nov 01, 2018 at 11:34:29AM +, Mark Rutland wrote:
> On Thu, Nov 01, 2018 at 11:09:57PM +0800, Peng Hao wrote:
> > remove unnecessary header file init.h.
> >
> > Signed-off-by: Peng Hao
>
> Acked-by: Mark Rutland
... though please fix the title:
s/revmove/remove/
Mark.
On Thu, Nov 01, 2018 at 11:09:57PM +0800, Peng Hao wrote:
> remove unnecessary header file init.h.
>
> Signed-off-by: Peng Hao
Acked-by: Mark Rutland
Mark.
> ---
> drivers/misc/pvpanic.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/misc/pvpanic.c
o have a trailing
comma.
This patch removes the redundant comma.
... with that commit message (and the title fixed to say 'comma' rather
than 'semicolon':
Acked-by: Mark Rutland
Either that, or simply drop this patch entirely.
Thanks,
Mark.
>
> Signed-off-b
On Wed, Oct 31, 2018 at 09:37:17PM +0800, Peng Hao wrote:
> move pvpanic.c from drivers/platform/x86 to drivers/misc.
> following patches will use pvpanic device in arm64.
FWIW, the series as a whole looks fine to me, so for all patches:
Acked-by: Mark Rutland
Thanks,
Mark.
>
> S
On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote:
> On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote:
> > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
> >> + *
> >> + * L3 Tile and DMC channel selection is through
On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote:
> Hi Ganapat,
>
>
> Sorry for the delay in replying; I was away most of last week.
>
> On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote:
> > On Sat, May 5, 2018 at 12:16 AM, Ganapat
Hi Ganapat,
Sorry for the delay in replying; I was away most of last week.
On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote:
> On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni
> wrote:
> > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote:
> >>
Hi Kim,
On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote:
> On Wed, 25 Apr 2018 14:30:47 +0530
> Ganapatrao Kulkarni wrote:
>
> > +static int thunderx2_uncore_event_init(struct perf_event *event)
> This PMU driver can be made more user-friendly by not just silently
> returning an er
Hi,
On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
> +
> +/* L3c and DMC has 16 and 8 channels per socket respectively.
> + * Each Channel supports UNCORE PMU device and consists of
> + * 4 independent programmable counters. Counters are 32 bit
> + * and does not support over
On Thu, Oct 19, 2017 at 04:28:35PM +0100, Will Deacon wrote:
> On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote:
> > Will, are you happy to queue this?
> >
> > There's a minor fixup [1] needed in patch 2, but otherwise this looks
> > good to me, a
Will, are you happy to queue this?
There's a minor fixup [1] needed in patch 2, but otherwise this looks
good to me, and builds cleanly.
I've pushed out a branch [2] with that fix folded in, in case that's
easier for you. Otherwise, feel free to pick these up with my Ack.
Thanks,
Mark.
[1]
htt
On Thu, Oct 19, 2017 at 07:05:17PM +0800, Shaokun Zhang wrote:
> This patch adds support HiSilicon SoC uncore PMU driver framework and
> interfaces.
> +static bool hisi_validate_event_group(struct perf_event *event)
> +{
> + struct perf_event *sibling, *leader = event->group_leader;
> + st
On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
> On 2017/10/17 23:16, Mark Rutland wrote:
> > On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> >> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
> >> +
On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
> DDRC has own control, counter and interrupt registers and is an separate
> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
> mapped to 8
On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has
On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
> + struct platform_device *pdev)
> +{
> + int irq, ret;
> +
> + /* Read and init IRQ */
> + irq = platform_get_irq(pdev, 0);
> +
Hi,
Apologies for the delay for this review.
Largely this seems to look OK, but there are a couple of things which
stick out.
On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
> +int hisi_uncore_pmu_event_init(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event
On Tue, Jul 25, 2017 at 08:10:41PM +0800, Shaokun Zhang wrote:
> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
> DDRC has own control, counter and interrupt registers and is an separate
> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
> mapped to 8
On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote:
> +/* HHA register definition */
> +#define HHA_INT_MASK 0x0804
> +#define HHA_INT_STATUS 0x0808
> +#define HHA_INT_CLEAR0x080C
> +#define HHA_PERF_CTRL0x1E00
> +#define HHA_EVENT_CT
On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote:
> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
> L3C has own control, counter and interrupt registers and is an separate
> PMU. For each L3C PMU, it has 8-programable counters and supports 0x60
> events, event
Hi,
On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote:
> +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
> +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
> +{
> + u64 mpidr;
> +
> + mpidr = read_cpuid_mpidr();
> + if (mpidr & MPIDR_MT_BITMASK) {
Hi,
On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Shaokun Zhang
> Signed-off-by: Anurup M
> ---
> Documentation/perf/hisi-pmu.txt | 52
> +
On Thu, Jun 22, 2017 at 06:52:56PM +0100, Mark Rutland wrote:
> Hi Hoan,
>
> This largely looks good; I have one minor comment.
>
> On Tue, Jun 06, 2017 at 11:02:26AM -0700, Hoan Tran wrote:
> > static inline void
> > +xgene_pmu_write_counter64(struct xgene_pmu_dev
On Thu, Jun 22, 2017 at 11:13:08AM -0700, Hoan Tran wrote:
> On Thu, Jun 22, 2017 at 10:52 AM, Mark Rutland wrote:
> > On Tue, Jun 06, 2017 at 11:02:26AM -0700, Hoan Tran wrote:
> > > static inline void
> > > +xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_d
int idx)
> {
> - return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
> + return (u64)readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
> }
Nit: the cast is redundant, and can go.
Otherwise:
Acked-by: Mark Rutland
Thanks,
Mark.
--
To unsubscribe
s->start_counters() just
before releasing it.
With that:
Acked-by: Mark Rutland
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe linux-doc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
> + const struct acpi_device_id *id;
> +
Since this was the subject of confusion before, can we please add a
comment here, e.g.
/*
* We have to iterate over the list as acpi_match_device_ids()
* doesn't tell us *which* entry matches, and there's no help
On Fri, Jun 02, 2017 at 09:54:32AM -0700, Hoan Tran wrote:
> On Fri, Jun 2, 2017 at 7:59 AM, Mark Rutland wrote:
> > On Mon, Apr 03, 2017 at 09:47:55AM -0700, Hoan Tran wrote:
> >> +static const struct acpi_device_id *xgene_pmu_acpi_match_type(
> >> +
Hi Hoan,
Apologies for the delay in getting to this.
On Mon, Apr 03, 2017 at 09:47:57AM -0700, Hoan Tran wrote:
> This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
> Unit version 3.
>
> It can support up to
> - 2 IOB PMU instances
> - 8 L3C PMU instances
> - 2 MCB PMU i
_acpi_type_match, adev);
> + if (!acpi_id)
> + return AE_OK;
As above, and as I covered in my reply to v1, I think the above should
be:
acpi_id = acpi_match_device_ids(adev, xgene_pmu_acpi_type_match);
if (!acpi_id)
return AE_OK;
... or am I miss
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
> +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
[...]
> +The current driver doesnot support sampling. so "perf record" is unsupported.
Nit: spacing
Otherwise, t
On Tue, Mar 14, 2017 at 11:06:52AM -0700, Hoan Tran wrote:
> This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
> Unit in the next generation of X-Gene SoC.
>
> Signed-off-by: Hoan Tran
> ---
> drivers/perf/xgene_pmu.c | 645
> ++
On Tue, Mar 14, 2017 at 11:06:51AM -0700, Hoan Tran wrote:
> This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
> Unit in the next generation of X-Gene SoC.
It adds a description, certainly.
>
> Signed-off-by: Hoan Tran
> ---
> Documentation/perf/xgene-pmu.txt | 17 ++
On Thu, Feb 16, 2017 at 05:08:20PM -0800, Kees Cook wrote:
> On Thu, Feb 16, 2017 at 2:25 PM, Pavel Machek wrote:
> > Hi!
> >
> >>
> >> -config DEBUG_RODATA
> >> +config STRICT_KERNEL_RWX
> >> bool "Make kernel text and rodata read-only" if
> >> ARCH_OPTIONAL_KERNEL_RWX
> >> depends o
h->oem_revision == 0)
> + return true;
> +
> + return false;
> +}
> +
> /**
> * parse_spcr() - parse ACPI SPCR table and add preferred console
> *
> @@ -93,6 +113,9 @@ int __init parse_spcr(bool earlycon)
> goto done;
> }
&g
;
> if (!memcmp(id, "QDF2000 ", ACPI_OEM_TABLE_ID_SIZE) &&
> h->oem_revision == 0)
> return True;
>
> return False;
> }
s/False/false/g
s/True/true/g
With that, this looks fine to me. I'm not too familiar w
On Wed, Feb 08, 2017 at 07:27:29AM -0600, Timur Tabi wrote:
> Robin Murphy wrote:
> >Are we to take it that every SoC now and always with any Kryo or Falkor
> >core which also has an SBSA UART will require this workaround?
>
> No, only Kryo and Falkor V1 based SOCs have this problem. Falkor V2
>
> options do.
>
> Signed-off-by: Laura Abbott
As with patch 1, this looks good to me. FWIW:
Acked-by: Mark Rutland
> diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
> index 939815e..560a8d8 100644
> --- a/arch/arm64/Kconfig.debug
> +++ b/arch/arm64/Kconfig
d make these options def_bool y for almost all of those
> arches.
>
> Signed-off-by: Laura Abbott
>From my POV this looks good. FWIW:
Acked-by: Mark Rutland
Mark.
> ---
> v2: This patch is now doing just the refactor of the existing config options.
> ---
off-by: Christopher Covington
This looks simple, self-contained, and correct, so FWIW:
Acked-by: Mark Rutland
Catalin/Will, since we may see a documentation conflict against a timer
erratum, would you be hapyp to pick up [1] first, fixing up this patch
as necessary?
[1]
http://lists.infradead.o
On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
> is triggered, page table entries using the new translation table base
>
Hi,
On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote:
> On 01/27/2017 09:38 AM, Mark Rutland wrote:
> > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
> >> Replacing the above sequence with the one below will ensure that no TLB
&g
On Fri, Jan 27, 2017 at 02:38:49PM +, Mark Rutland wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose
> the con
On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
> is triggered, page table entries using the new translation table base
>
Hi,
On Wed, Jan 18, 2017 at 05:29:06PM -0800, Laura Abbott wrote:
>
> Despite the word 'debug' in CONFIG_DEBUG_SET_MODULE_RONX, this kernel
> option provides key security features that are to be expected on a
> modern system. Change the name to CONFIG_HARDENED_MODULE_MAPPINGS which
> more accurat
Hi Laura,
On Wed, Jan 18, 2017 at 05:29:05PM -0800, Laura Abbott wrote:
>
> Despite the word 'debug' in CONFIG_DEBUG_RODATA, this kernel option
> provides key security features that are to be expected on a modern
> system. Change the name to CONFIG_HARDENED_PAGE_MAPPINGS which more
> accurately d
On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote:
> On Wed, Jan 11, 2017 at 06:40:52PM +0000, Mark Rutland wrote:
> > Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0().
>
> This may be fine if my assumptions about this erratum are co
On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote:
> On 01/11/2017 12:37 PM, Mark Rutland wrote:
> >The name, as it is, is perfectly descriptive.
> >
> >Let's not sacrifice legibility over a non-issue.
>
> I don't want to kick a dead
On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote:
> On 11/01/17 18:06, Catalin Marinas wrote:
> > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> >> index 32682be..9ee46df 100644
> >> --- a/arch/arm64
On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote:
> On 01/11/2017 12:33 PM, Mark Rutland wrote:
> >It'll need to affect all lines since the kconfig column needs to expand
> >by at least one character to fit QCOM_FALKOR_ERRATUM_1003.
>
> Or we can make the macro
On Wed, Jan 11, 2017 at 06:06:27PM +, Catalin Marinas wrote:
> On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> > -| Implementor| Component | Erratum ID | Kconfig
> > |
> > +| Implementor | Component | Erratum ID | Kconfig
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
> +The Hisilicon SoC HiP05/06/07 chips consist of various independent system
> +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
> +These PMU devices are independent and have hardware logic to gather
> +statistics and performa
Hi,
On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
> +config QCOM_FALKOR_E1003_RESERVED_ASID
> + int
> + default 1
> + depends on QCOM_FALKOR_ERRATUM_1003
> +
I don't think this needs to be configurable, so let's drop this into a
header, e.g. drop:
#define FAL
() macros as appropriate.
Signed-off-by: Mark Rutland
Cc: Boqun Feng
Cc: Jonathan Corbet
Cc: Paul E. McKenney
Cc: Peter Zijlstra
Cc: Will Deacon
Cc: linux-doc@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
Documentation/atomic_ops.txt | 18 +-
1 file changed, 9 insertions
ACCESS_ONCE() is only used in a reader context in the
circular buffer documentation.
Signed-off-by: Mark Rutland
Cc: David Howells
Cc: Jonathan Corbet
Cc: Paul E. McKenney
Cc: linux-doc@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
Documentation/circular-buffers.txt | 4 ++--
1 file
On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:
> On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> >>+ - scl-id : The Super Cluster ID. This can be the ID of the CPU die
> >>+
On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote:
> On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
> >>diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> >>
On Thu, Nov 03, 2016 at 01:42:03AM -0400, Anurup M wrote:
> + do {
> + /* Get count from individual L3C banks and sum them up */
> + for (i = 0; i < num_banks; i++) {
> + total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data,
> +
Hi,
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
>
> Signed-off-by: Anurup M
> Signed-off-by: Shaokun Zhang
> ---
> .../devicetree/bindings/arm/hisilicon/pmu.txt
On Thu, Nov 03, 2016 at 01:41:59AM -0400, Anurup M wrote:
> From: Tan Xiaojun
>
> The Hisilicon Djtag is an independent component which connects
> with some other components in the SoC by Debug Bus. This driver
> can be configured to access the registers of connecting components
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