On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote: > This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each > DDRC has own control, counter and interrupt registers and is an separate > PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been > mapped to 8-events by hardware, it assumes that counter index is equal > to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to > handle counter (32-bits) overflow. > > Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com> > Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> > Signed-off-by: Anurup M <anuru...@huawei.com>
I have the same comments for this case as for the other two PMU drivers. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
