On 3/27/2024 3:50 PM, Jakub Kicinski wrote:
On Wed, 27 Mar 2024 09:25:31 -0400 Mateusz Polchlopek wrote:
v2:
- fixed warning related to wrong specifier to dev_err_once in
commit 7
- fixed warnings related to unused variables in commit 9
You posted this yesterday and got no feedback.
You'
E825C products have a different PHY model than E822, E823 and E810 products.
This PHY is ETH56G and its support is necessary to have functional PTP stack
for E825C products.
Grzegorz Nitka (2):
ice: Add NAC Topology device capability parser
ice: Adjust PTP init for 2x50G E825C devices
Jacob K
Create new ice_ptp_hw struct and use it for all HW and PTP-related
fields from struct ice_hw.
Replace definitions with struct fields, which values are set accordingly
to a specific device.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
driver
From: Jacob Keller
Multiple places in the driver code need to convert enum ice_ptp_tmr_cmd
values into register bits for both the main timer and the PHY port
timers. The main MAC register has one bit scheme for timer commands,
while the PHY commands use a different scheme.
The E810 and E830 devi
From: Sergey Temerkhanov
Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 63
Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 11 ---
drivers/net/ethernet/int
From: Sergey Temerkhanov
Move CGU block to the beginning of ice_ptp_hw.c
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 986 ++--
1 file change
From: Jacob Keller
Add a new helper for getting base clock increment value for specific HW.
Signed-off-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 7 +--
drivers/net/et
Simplify the code by using anonymous struct in CGU registers instead of
naming each structure 'field'.
Suggested-by: Przemek Kitszel
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 12 ++---
dri
From: Sergey Temerkhanov
E825C products feature a new PHY model - ETH56G.
Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
analogous to E82X and E810 ones with addition of a few HW-specific
functionalities for ETH56G like one-step timestamping.
It ensures correct PTP ini
From: Michal Michalik
The CGU layout of E825-C is a little different than E822/E823. Add
support the new hardware adding relevant functions.
Signed-off-by: Michal Michalik
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet
From: Grzegorz Nitka
Add new device capability ICE_AQC_CAPS_NAC_TOPOLOGY which allows to
determine the mode of operation (1 or 2 NAC).
Define a new structure to store data from new capability and
corresponding parser code.
Co-developed-by: Prathisna Padmasanan
Signed-off-by: Prathisna Padmasana
There are E825C products featuring 2 NACs. Those have only one source
clock on the primary NAC.
For those devices, there
should be only one clock controller on the primary NAC. All PFs from
both NACs should connect as auxiliary devices to the auxiliary driver on
the primary NAC.
Reviewed-by: Igor
From: Grzegorz Nitka
>From FW/HW perspective, 2 port topology in E825C devices requires
merging of 2 port mapping internally to CPK and breakout mapping
externally to CPK. As a consequence, it requires different port
numbering from PTP code perspective.
For that topology, pf_id can not be used to
On 3/27/24 15:22, Alexander Lobakin wrote:
Some structures contain flexible arrays at the end and the counter for
them, but the counter has explicit Endianness and thus __counted_by()
can't be used directly.
To increase test coverage for potential problems without breaking
anything, introduce __
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Swiatkowski
> Sent: Tuesday, March 26, 2024 3:05 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Loktionov, Aleksandr ;
> net...@vger.kernel.org; Michal Swiatkowski
>
> Subject: [Intel-wired-lan] [iwl-next v1 1/3] ice:
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Swiatkowski
> Sent: Tuesday, March 26, 2024 3:05 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Drewek, Wojciech ; net...@vger.kernel.org;
> Michal Swiatkowski ; Piotr Raczynski
> ; Kitszel, Przemyslaw
>
> Subject: [I
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Swiatkowski
> Sent: Tuesday, March 26, 2024 3:05 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Drewek, Wojciech ; net...@vger.kernel.org;
> Jiri Pirko ; Michal Swiatkowski
>
> Subject: [Intel-wired-lan] [iwl-next v1 3
Hi,
> > +/**
> > + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
> > + * @hw: pointer to the HW struct
> > + * @quad: the timestamp quad
> > + * @ena: enable or disable interrupt
> > + * @threshold: interrupt threshold
> > + *
> > + * Configure TX timestamp interrupt for the specified
On Tue, Mar 26, 2024 at 09:02:12PM -0700, Jakub Kicinski wrote:
> __napi_alloc_skb() is napi_alloc_skb() with the added flexibility
> of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is
> implied. The only practical choice the caller has is whether to
> set __GFP_NOWARN. But that's a fa
On Tue, Mar 26, 2024 at 02:34:54PM +0100, Kurt Kanzenbach wrote:
> Add support for offloading MQPRIO. The hardware has four priorities as well
> as four queues. Each queue must be a assigned with a unique priority.
>
> However, the priorities are only considered in TSN Tx mode. There are two
> TSN
On Thu, Mar 28, 2024 at 12:32 PM Simon Horman wrote:
>
> On Tue, Mar 26, 2024 at 09:02:12PM -0700, Jakub Kicinski wrote:
> > __napi_alloc_skb() is napi_alloc_skb() with the added flexibility
> > of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is
> > implied. The only practical choice
gcc
i386 allyesconfig gcc
i386 buildonly-randconfig-001-20240328 gcc
i386 buildonly-randconfig-002-20240328 gcc
i386 buildonly-randconfig-003-20240328 clang
i386 buildonly-randconfig-004-20240328 gcc
i386 buildonly-randconfig-005-20240328
Currently most of the API for page_frag API is returning
'virtual address' as output or expecting 'virtual address'
as input, in order to differentiate the API handling between
'virtual address' and 'struct page', add '_va' suffix to the
corresponding API mirroring the page_pool_alloc_va() API of
t
allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20240328 gcc
arc randconfig-002-20240328 gcc
arm
allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20240328 gcc
arc randconfig-002-20240328 gcc
arm allmodconfig
On Thu, Mar 28, 2024 at 3:04 PM Karol Kolacinski
wrote:
>
> From: Sergey Temerkhanov
>
> Introduce functions enabling/disabling Tx TS interrupts
> for the E822 and ETH56G PHYs
>
> Signed-off-by: Sergey Temerkhanov
> Reviewed-by: Przemek Kitszel
> Reviewed-by: Arkadiusz Kubalewski
> Signed-off-
allmodconfig gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc haps_hs_smp_defconfig gcc
arc randconfig-001-20240328 gcc
arc
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Brett Creeley
> Sent: Thursday, March 14, 2024 4:54 PM
> To: ivecera ; net...@vger.kernel.org
> Cc: moderated list:INTEL ETHERNET DRIVERS l...@lists.osuosl.org>; open list ; Loktionov,
> Aleksandr ; Eric Dumazet
> ; Nguyen, Antho
On Wed, Mar 27, 2024 at 08:57:28AM +0100, Ivan Vecera wrote:
> Commit 0ef2d5afb12d ("i40e: KISS the client interface") simplified
> the client interface so in practice it supports only one client
> per i40e netdev. But we have still 2 notification functions that
> uses as parameter a pointer to VSI
On Wed, Mar 27, 2024 at 08:57:27AM +0100, Ivan Vecera wrote:
> The field is initialized always to zero and it is never read.
> Remove it.
>
> Reviewed-by: Michal Schmidt
> Reviewed-by: Aleksandr Loktionov
> Reviewed-by: Kalesh AP
> Signed-off-by: Ivan Vecera
Reviewed-by: Simon Horman
On Wed, Mar 27, 2024 at 08:57:29AM +0100, Ivan Vecera wrote:
> Commit 07d44190a389 ("i40e/i40evf: Detect and recover hung queue
> scenario") changes i40e_detect_recover_hung() argument type from
> i40e_pf* to i40e_vsi* to be shareable by both i40e and i40evf.
> Because the i40evf does not exist any
On Wed, Mar 27, 2024 at 08:57:30AM +0100, Ivan Vecera wrote:
> Add simple helper i40e_pf_get_main_vsi(pf) to access main VSI
> that replaces pattern 'pf->vsi[pf->lan_vsi]'
>
> Reviewed-by: Michal Schmidt
> Signed-off-by: Ivan Vecera
Reviewed-by: Simon Horman
On Wed, Mar 27, 2024 at 08:57:31AM +0100, Ivan Vecera wrote:
> In the driver code there are 3 types of checks whether given
> VSI is main or not:
> 1. vsi->type ==/!= I40E_VSI_MAIN
> 2. vsi ==/!= pf->vsi[pf->lan_vsi]
> 3. vsi->seid ==/!= pf->vsi[pf->lan_vsi]->seid
>
> All of them are equivalent an
On Wed, Mar 27, 2024 at 08:57:32AM +0100, Ivan Vecera wrote:
> Add a helper to access main VEB:
>
> i40e_pf_get_main_veb(pf) replaces 'pf->veb[pf->lan_veb]'
>
> Reviewed-by: Michal Schmidt
> Reviewed-by: Aleksandr Loktionov
> Signed-off-by: Ivan Vecera
Reviewed-by: Simon Horman
On Wed, Mar 27, 2024 at 08:57:33AM +0100, Ivan Vecera wrote:
> Add helper i40e_vsi_reconfig_tc(vsi) that configures TC
> for given VSI using previously stored TC bitmap.
>
> Effectively replaces open-coded patterns:
>
> enabled_tc = vsi->tc_config.enabled_tc;
> vsi->tc_config.enabled_tc = 0;
> i4
On Tue, Mar 26, 2024 at 05:44:55PM +0100, Marcin Szycik wrote:
> In cases when VF sends malformed packets that are classified as malicious,
> sometimes it causes Tx queue to freeze. This frozen queue can be stuck
> for several minutes being unusable. This behavior can be reproduced with
> a faulty
On 3/26/2024 9:36 AM, Paul Greenwalt wrote:
Update existing E830 device ids and comments to align with new naming 'C'
for 100G and 'CC' for 200G.
Reviewed-by: Wojciech Drewek
Signed-off-by: Paul Greenwalt
---
...
diff --git a/drivers/net/ethernet/intel/ice/ice_devids.h
b/drivers/net/et
> On Mar 28, 2024, at 2:16 PM, Tony Nguyen wrote:
>
>> +/* Intel(R) Ethernet Controller E830-CC for SFP-DD */
>> +#define ICE_DEV_ID_E83CC0_SFP_DD 0x12D4
>
> This doesn't compile; there's a stray '0' here.
Not stray, just mispositioned in the definition above.
> ../drivers/net/ethernet/intel/i
On 3/26/2024 7:30 AM, Mateusz Polchlopek wrote:
For performance reasons there is a need to have support for selectable
Tx scheduler topology. Currently firmware supports only the default
9-layer and 5-layer topology. This patch series enables switch from
default to 5-layer topology, if user de
On 3/28/2024 2:37 PM, Rustad, Mark D wrote:
On Mar 28, 2024, at 2:16 PM, Tony Nguyen wrote:
+/* Intel(R) Ethernet Controller E830-CC for SFP-DD */
+#define ICE_DEV_ID_E83CC0_SFP_DD 0x12D4
This doesn't compile; there's a stray '0' here.
Not stray, just mispositioned in the definition abo
Add support for additional E830 device ids which are supported by the
driver:
- 0x12D5: Intel(R) Ethernet Controller E830-C for backplane
- 0x12D8: Intel(R) Ethernet Controller E830-C for QSFP
- 0x12DA: Intel(R) Ethernet Controller E830-C for SFP
- 0x12DC: Intel(R) Ethernet Controller E830-XXV for
Update existing E830 device ids and comments to align with new naming 'C'
for 100G and 'CC' for 200G.
Reviewed-by: Wojciech Drewek
Signed-off-by: Paul Greenwalt
---
v2 -> v3: fix compiler error
---
drivers/net/ethernet/intel/ice/ice_common.c | 8
drivers/net/ethernet/intel/ice/ice_dev
Hello:
This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski :
On Tue, 26 Mar 2024 21:02:12 -0700 you wrote:
> __napi_alloc_skb() is napi_alloc_skb() with the added flexibility
> of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is
> implied. The only practical choice
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski :
On Wed, 27 Mar 2024 15:22:38 +0100 you wrote:
> Some structures contain flexible arrays at the end and the counter for
> them, but the counter has explicit Endianness and thus __counted_by()
> can't be used directly.
On Wed, Mar 27, 2024 at 1:28 PM Ivan Vecera wrote:
>
> Commit 07d44190a389 ("i40e/i40evf: Detect and recover hung queue
> scenario") changes i40e_detect_recover_hung() argument type from
> i40e_pf* to i40e_vsi* to be shareable by both i40e and i40evf.
> Because the i40evf does not exist anymore an
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Schmidt
> Sent: Tuesday, March 26, 2024 4:51 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Jiri Pirko ; Temerkhanov, Sergey
> ; net...@vger.kernel.org; Richard Cochran
> ; Kubalewski, Arkadiusz
> ; Kolacinski, Karol
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Schmidt
> Sent: Tuesday, March 26, 2024 4:51 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Jiri Pirko ; Temerkhanov, Sergey
> ; net...@vger.kernel.org; Richard Cochran
> ; Kubalewski, Arkadiusz
> ; Kolacinski, Karol
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Schmidt
> Sent: Tuesday, March 26, 2024 4:51 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Jiri Pirko ; Temerkhanov, Sergey
> ; net...@vger.kernel.org; Richard Cochran
> ; Kubalewski, Arkadiusz
> ; Kolacinski, Karol
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