arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231011 gcc
arm allmodconfig gcc
arm
gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231011 gcc
arm allmodconfig gcc
arm
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231011 gcc
arm allmodconfig gcc
arm
allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231011 gcc
arm allmodconfig gcc
arm
On Tue, Oct 10, 2023 at 5:34 PM Ahmed Zaki wrote:
>
>
> On 2023-10-10 14:40, Willem de Bruijn wrote:
>
> On Tue, Oct 10, 2023 at 4:05 PM Ahmed Zaki wrote:
>
> Symmetric RSS hash functions are beneficial in applications that monitor
> both Tx and Rx packets of the same flow (IDS, software firewall
On Mon, Sep 18, 2023 at 04:10:55PM +0300, Ilpo Järvinen wrote:
> pci_disable_link_state() lacks a symmetric pair. Some drivers want to
> disable ASPM during certain phases of their operation but then
> re-enable it later on. If pci_disable_link_state() is made for the
> device, there is currently n
On Mon, Sep 18, 2023 at 04:10:53PM +0300, Ilpo Järvinen wrote:
> PCI core/ASPM service driver allows controlling ASPM state through
> pci_disable_link_state() and pci_enable_link_state() API. It was
> decided earlier (see the Link below), to not allow ASPM changes when OS
> does not have control ov
On 10/11/2023 4:02 AM, Karol Kolacinski wrote:
> When settime is called, the driver tries to disable the PHY to avoid
> PHY clock running and giving incorrect timestamps during time change.
> PHY stop procedure takes more HW writes than just marking timestamps as
> invalid. After settime, the PHYs
On 10/11/2023 4:04 AM, Karol Kolacinski wrote:
> During reset, TX_TSYN interrupt should be processed as it may process
> timestamps in brief moments before and after reset.
> Timestamping should be enabled on VSIs at the end of reset procedure.
> On ice_get_phy_tx_tstamp_ready error, interrupt s
On Mon, Sep 18, 2023 at 04:10:53PM +0300, Ilpo Järvinen wrote:
> PCI core/ASPM service driver allows controlling ASPM state through
> pci_disable_link_state() and pci_enable_link_state() API. It was
> decided earlier (see the Link below), to not allow ASPM changes when OS
> does not have control ov
On Mon, Sep 18, 2023 at 04:10:54PM +0300, Ilpo Järvinen wrote:
> ASPM service driver does the same L0S / L1S / sub states allowed
> calculation in __pci_disable_link_state() and
> pci_set_default_link_state().
Is there a typo or something here? This patch only adds a call to
__pci_disable_link_st
On Wed, 11 Oct 2023 14:25:55 +0900 takeru hayasaka wrote:
> > Regarding the patch - you are only adding flow types, not a new field
> > (which are defined as RXH_*). If we want to hash on an extra field,
> > I think we need to specify that field as well?
>
> I've been really struggling with this
Wed, Oct 11, 2023 at 03:13:47PM CEST, pawel.chmielew...@intel.com wrote:
>From: Paul Greenwalt
>
>The need to map Ethtool forced speeds to Ethtool supported link modes is
>common among drivers. To support this, add a common structure for forced
>speed maps and a function to init them. This is sol
[ Resend - rejected by netdev and linux-doc MLs for HTML content]
On 2023-10-10 14:40, Willem de Bruijn wrote:
On Tue, Oct 10, 2023 at 4:05 PM Ahmed Zaki wrote:
Symmetric RSS hash functions are beneficial in applications that monitor
both Tx and Rx packets of the same flow (IDS, software fir
Refactor ice_get_link_ksettings to using forced speed to link modes mapping.
Suggested-by : Alexander Lobakin
Reviewed-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Signed-off-by: Paul Greenwalt
Signed-off-by: Pawel Chmielewski
---
drivers/net/ethernet/intel/ice/ice.h | 1 +
driver
From: Paul Greenwalt
The need to map Ethtool forced speeds to Ethtool supported link modes is
common among drivers. To support this, add a common structure for forced
speed maps and a function to init them. This is solution was originally
introduced in commit 1d4e4ecccb11 ("qede: populate suppor
The following patch set was initially a part of [1]. As the purpose of
the original series was to add the support of the new hardware to the
intel ice driver, the refactoring of advertised link modes mapping was
extracted to a new set.
The patch set adds a common mechanism for mapping Ethtool force
Wed, Oct 11, 2023 at 12:12:31PM CEST, arkadiusz.kubalew...@intel.com wrote:
>Improve monitoring and control over dpll devices.
>Allow user to receive measurement of phase difference between signals
>on pin and dpll (phase-offset).
>Allow user to receive and control adjustable value of pin's signal
During reset, TX_TSYN interrupt should be processed as it may process
timestamps in brief moments before and after reset.
Timestamping should be enabled on VSIs at the end of reset procedure.
On ice_get_phy_tx_tstamp_ready error, interrupt should not be rearmed,
because error only happens on resets
When settime is called, the driver tries to disable the PHY to avoid
PHY clock running and giving incorrect timestamps during time change.
PHY stop procedure takes more HW writes than just marking timestamps as
invalid. After settime, the PHYs is recalibrated and timestamping is
reenabled.
Change d
> -Original Message-
> From: Lobakin, Aleksander
> Sent: Wednesday, October 11, 2023 11:25 AM
> To: Loktionov, Aleksandr
> Cc: intel-wired-...@lists.osuosl.org; Nguyen, Anthony L
> ; Jagielski, Jedrzej
> Subject: Re: [Intel-wired-lan] [PATCH iwl-next v2] i40e: add restore default
> s
>From: Jakub Kicinski
>Sent: Wednesday, October 11, 2023 4:35 AM
>
>On Tue, 10 Oct 2023 00:26:11 +0200 Arkadiusz Kubalewski wrote:
>> Improve monitoring and control over dpll devices.
>> Allow user to receive measurement of phase difference between signals
>> on pin and dpll (phase-offset).
>> All
Align the approach of pin frequency set behavior with the approach
introduced with pin phase adjust set.
Fail the request if any of devices did not registered the callback ops.
If callback op on any pin's registered device fails, return error and
rollback the value to previous one.
Signed-off-by:
Implement new callback ops related to measurement and adjustment of
signal phase for pin-dpll in ice driver.
Signed-off-by: Arkadiusz Kubalewski
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 220 +-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
2 files changed, 226 in
Add callback ops for pin-dpll phase measurement.
Add callback for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke callbacks in dpll_netlink.c when filling the pin details to
provide user with phase related attribute values.
Signed-off-by: Arkadiusz Kub
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal
Signed-off-by: Arkadiusz Kubalewski
---
Documentation/netlink/specs/dpll.yaml | 30 +++
drivers/dpll/dpll_nl.c
Add documentation on:
- measurement of phase of signal between pin and dpll
- adjustment of pin signal phase
Signed-off-by: Arkadiusz Kubalewski
---
Documentation/driver-api/dpll.rst | 53 ++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation
Improve monitoring and control over dpll devices.
Allow user to receive measurement of phase difference between signals
on pin and dpll (phase-offset).
Allow user to receive and control adjustable value of pin's signal
phase (phase-adjust).
v4->v5:
- rebase series on top of net-next/main, fix conf
From: Alexander Lobakin
Date: Wed, 11 Oct 2023 11:22:21 +0200
> From: Aleksandr Loktionov
> Date: Wed, 11 Oct 2023 11:13:42 +0200
>
> Please add netdev and linux-kernel MLs to CCs when sending the next version.
>
>> In order to avoid no link after plugging a different type PHY module.
>
> The
From: Aleksandr Loktionov
Date: Wed, 11 Oct 2023 11:13:42 +0200
Please add netdev and linux-kernel MLs to CCs when sending the next version.
> In order to avoid no link after plugging a different type PHY module.
The sentence is incomplete, it tells "why", but no "what".
>
> Add reset link sp
In order to avoid no link after plugging a different type PHY module.
Add reset link speed settings to the default values for PHY module,
if different PHY module is inserted and currently defined user-specified
speed is not compatible with this module.
Reviewed-by: Jedrzej Jagielski
Signed-off-b
On Wed, Oct 11, 2023 at 10:05:06AM +0200, Aleksandr Loktionov wrote:
> In order to avoid no link after plugging a different type PHY module.
>
> Add reset link speed settings to the default values for PHY module,
> if different PHY module is inserted and currently defined user-specified
> speed is
In order to avoid no link after plugging a different type PHY module.
Add reset link speed settings to the default values for PHY module,
if different PHY module is inserted and currently defined user-specified
speed is not compatible with this module.
Signed-off-by: Radoslaw Tyl
Signed-off-by:
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Dave Ertman
> Sent: Tuesday, October 10, 2023 7:32 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: net...@vger.kernel.org
> Subject: [Intel-wired-lan] [PATCH iwl-next v2] ice: Fix SRIOV LAG disable on
> non-compliant aggreagate
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