till means disabled
> and "1" means enabled with full support and maximum power savings.
>
> v2: Use positive value instead of negative for different operation mode
> as suggested by Daniel.
>
> Cc: Paulo Zanoni
> Cc: Daniel Vetter
> Signed-off-by:
fd, bo, tiling_b, tiling_b ==
> I915_TILING_Y ? 128 : 512) == 0);
> + igt_require(__gem_set_tiling(fd, bo, tiling_b,
> tile_width(devid, tiling_b)) == 0);
> b = __gem_mmap__gtt(fd, bo, huge_object_size, PROT_READ | PROT_WRITE);
> igt_require(b);
>
2015-12-15 19:08 GMT-02:00 Ville Syrjälä :
> On Tue, Dec 15, 2015 at 06:51:56PM -0200, Paulo Zanoni wrote:
>> 2015-12-14 18:15 GMT-02:00 :
>> > From: Ville Syrjälä
>> >
>> > Gen2/3 platforms have some unusual tile dimensions. Account
>>
Em Sex, 2016-10-14 às 16:47 -0700, Anusha Srivatsa escreveu:
> i915.enable_guc_loading/submission=2 forces the usage of GuC.
> For platforms that do not have a GuC, asking the kernel to use a GuC
> should not result in an error state. Do extra checks to see if the
> platform even has a GuC or not,
):
- Rebase
Reviewed-by: Maarten Lankhorst
Reviewed-by: Paulo Zanoni (v2)
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Lyude
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_display.c | 14 ++-
drivers/gpu/drm/i915/intel_drv.h | 6 +-
gt; need this function to be reusable for the next patch.
>
> Changes since v1:
> - Fix accidental behavior change in the code that Paulo pointed out
Reviewed-by: Paulo Zanoni
I just submitted v4 of patch 5 solving the conflicts I created. With
that + this review, we can merge this serie
Em Qua, 2016-10-19 às 09:50 +0200, Daniel Vetter escreveu:
> On Tue, Oct 18, 2016 at 07:33:10PM +0300, Jani Nikula wrote:
> >
> > On Tue, 18 Oct 2016, Petri Latvala wrote:
> > >
> > > The current contributing docs for IGT state:
> > >
> > > <<
> > > There is no formal review requirement and r
Em Qua, 2016-10-12 às 15:28 +0200, Maarten Lankhorst escreveu:
> Caching is not required, drm_atomic_crtc_state_for_each_plane_state
> can be used to inspect all plane_states that are assigned to the
> current crtc_state, so we can just recalculate every time.
But can't the current for_each_plane_
-3425,29 +3424,28 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *cstate,
> > *
> > * FIXME: we may not allocate every single block here.
> > */
> > - total_data_rate =
> > skl_get_total_relative_data_rate(cstate);
> >
nce.
> >
> > Signed-off-by: Maarten Lankhorst > >
>
> Reviewed-by: Matt Roper
Reviewed-by: Paulo Zanoni
You could also get rid of the unsafe loop that computes alloc_size:
just do it in the main loop now that we iterate over everything. But
this can be done in a se
Em Qui, 2016-10-20 às 15:18 -0200, Paulo Zanoni escreveu:
> Em Qua, 2016-10-19 às 15:13 -0700, Matt Roper escreveu:
> >
> > On Wed, Oct 12, 2016 at 03:28:15PM +0200, Maarten Lankhorst wrote:
> > >
> > >
> > > It's only used in one function,
cate the cursor, it doesn't require extra
> allocation
> + * proportional to the data rate.
> + */
>
> - for (i = 0; i < PLANE_CURSOR; i++) {
> + for (i = 0; i < I915_MAX_PLANES; i++) {
As I mentioned earlier, this is also an unsaf
Em Qua, 2016-10-12 às 15:28 +0200, Maarten Lankhorst escreveu:
> Allow the driver to write watermarks during atomic evasion.
> This will make it possible to write the watermarks in a cleaner
> way on gen9+.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
e_wm(struct drm_crtc_state *cstate,
> struct skl_ddb_allocation *ddb, /* out
> */
> struct skl_pipe_wm *pipe_wm, /* out */
> + const struct skl_pipe_wm *old_pipe_wm,
> bool *changed /
stolen
Of course, you can only reproduce the bug if your screen is taller
than 2048 lines.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98213
Fixes: a98ee79317b4 ("drm/i915/fbc: enable FBC by default on HSW and BDW")
Cc: # v4.6+
Signed-off-by: Paulo Zanoni
---
drivers/gpu/
Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm
not aware of any real-world IGT failures caused by this.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
2 files changed, 9 insertions(
Em Seg, 2016-10-24 às 19:13 +0300, ville.syrj...@linux.intel.com
escreveu:
> From: Ville Syrjälä
>
> Pass the framebuffer size in .16 fixed point coordinates to
> drm_rect_rotate() since that's what the source coordinates are as
> well
> at this stage. We used to do this part of the computation i
wer. Power testing should really be done by the power management
team.
Due to the past situations we had, I'd like to see data on the
measurements done before I can believe that the problem is really FBC.
>
> Cc: Paulo Zanoni
> Cc: Marc Herbert
> Signed-off-by: Rodrigo
text would make
more sense if it was rewritten to:
Caching is not required, drm_atomic_crtc_state_for_each_plane_state can
be used to inspect the states of all planes assigned to the CRTC even
if they are not part of crtc_state, so we can just recalculate every
time.
But feel free to not use the te
continue;
> >
> > if (id != PLANE_CURSOR) {
> > DRM_DEBUG_ATOMIC("[PLANE:%d:plane
> > %d%c] ddb (%d - %d) -> (%d - %d)\n",
> > -
ce. (Paulo)
>
> Signed-off-by: Maarten Lankhorst
> Reviewed-by: Matt Roper
> Cc: Paulo Zanoni
I'd still prefer if you had used a safer way to loop through the
planes, not something that may just break when someone decides refactor
this code for the Nth time in the future and forget tha
gt; changes since v1:
> - Change comment to have a extra opening line. (Matt)
> - Rebase to remove unused plane->pipe == pipe, handled by the
> iterator
> now. (Paulo)
>
> Reviewed-by: Matt Roper
> Signed-off-by: Maarten Lankhorst
> Cc: Paulo Zanoni
Reviewed-by: Paulo Za
sed less than cursors,
> it's
> possible that this could help us uncover additional underruns that
> nobody had run across yet. Or it could have the opposite effect and
> eliminate some of the underruns that we haven't been able to get rid
> of
> yet.
>
> Cc: Bob Paa
to apply even on top of
Maarten's series. IMHO we should merge this soon, before patch 3 reach
its final form.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>
Em Qua, 2016-10-26 às 15:51 -0700, Matt Roper escreveu:
> This was the only use of (misleadingly-named) intel_num_planes()
> function, so we can remove it as well.
This one has a trivial conflict with Maarten's series. Same comment as
p1 regarding merging.
Reviewed-by: Paulo Zanoni
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> This patch make changes to use linetime latency instead of allocated
> DDB size during plane watermark calculation in switch case, This is
> required to implement new DDB allocation algorithm.
>
> In New Algorithm DDB is allocated based
ome
> planes are not added to the atomic state.
>
> Changes since v1:
> - Rephrase commit message. (Ville)
> - Use plane->base.id and plane->name to kill off cursor special
> case. (Matt)
Wasn't this Ville's suggestion? :)
> - Add intel_crtc to prevent a li
Em Qui, 2016-11-03 às 18:45 +0200, Ville Syrjälä escreveu:
> On Mon, Oct 17, 2016 at 02:37:15PM +0200, Maarten Lankhorst wrote:
> >
> > Signed-off-by: Maarten Lankhorst > >
> > ---
> > drivers/gpu/drm/i915/intel_fbc.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff
Em Qui, 2016-11-03 às 18:49 +0200, Ville Syrjälä escreveu:
> On Mon, Oct 17, 2016 at 02:37:16PM +0200, Maarten Lankhorst wrote:
> >
> > Signed-off-by: Maarten Lankhorst > >
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 12 ++--
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> >
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> This patch adds support to decode system memory bandwidth
> which will be used for arbitrated display memory percentage
> calculation in GEN9 based system.
>
> Changes from v1:
> - Address comments from Paulo
> - implement decode funct
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> This patch implemnets Workariunds related to display arbitrated
> memory
> bandwidth. These WA are applicabe for all gen-9 based platforms.
>
> Changes since v1:
> - Rebase on top of Paulo's patch series
> Changes since v2:
> - Rebase/
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> From: Mahesh Kumar
>
> Current code clears only plane ddb allocation if total ddb allocated
> to
> pipe in zero. y_plane ddb still contains old value, clear that as
> well.
>
> Signed-off-by: Mahesh Kumar
> ---
> drivers/gpu/drm/i915
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> From: Mahesh Kumar
>
> This patch adds variable to check for X_tiled & y_tiled planes,
> instead
> of always checking against framebuffer-modifiers.
>
> Changes:
> - Created separate patch as per Paulo's comment
> - Added x_tiled var
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> From: Mahesh Kumar
>
> This patch changes Watermak calculation to fixed point calculation.
> Problem with current calculation is during plane_blocks_per_line
> calculation we divide intermediate blocks with min_scanlines and
> takes flo
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> From: Mahesh Kumar
>
> This patch adds IPC support for platforms. This patch enables IPC
> only for BXT/KBL platform as for SKL recommendation is to keep is
> disabled.
> IPC (Isochronous Priority Control) is the hardware feature, which
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> From: Mahesh Kumar
>
> This patch implements new DDB allocation algorithm as per HW team
> recommendation. This algo takecare of scenario where we allocate less
> DDB
> for the planes with lower relative pixel rate, but they require mor
hat went
wrong here.
Cc: Jani Nikula
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c9..cc9e0c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/d
rent
interpretation, so I sent and email to the spec authors and got
clarification on the correct meaning. Also, BSpec was updated and
should be clear now.
Fixes: ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the memory bandwidth
WA")
Cc: sta...@vger.kernel.org
Cc: Mahesh Kumar
S
Em Qua, 2016-11-09 às 20:28 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
> On Monday 31 October 2016 11:33 PM, Paulo Zanoni wrote:
> >
> > Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> > >
> > > This patch make changes to use linetime latency
We can just call it earlier, so do it. The goal of the loop is to get
the plane's CRTC state, and we don't need it in order to call
intel_fbc_can_choose().
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
di
ad of iterating over all planes.
Cc: Ville Syrjälä
Reported-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_fbc.c | 36 +++-
2 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/d
Much simpler. Thanks to Ville for pointing this.
Cc: Ville Syrjälä
Reported-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu
Ville pointed out two ugly defects in the FBC code, and while trying
to fix them I spotted a few extra things. No real-world bugs fixed
here, but IMHO the code is much easier to read now.
Paulo Zanoni (7):
drm/i915/fbc: move the intel_fbc_can_choose() call out of the loop
drm/i915/fbc
and we'll more
consistently set the reason (e.g., if no primary planes are visible).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 33 +++--
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/
Use drm_atomic_get_existing_crtc_state() instead of looping through
the CRTC states and checking if the FBC CRTC is there.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915
Because it's shorter, easier to read, newer and cooler. And I don't
think anybody else has pending FBC patches right now, so the conflicts
should be minimal.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 26 +-
1 file changed, 13 inserti
Extract that part of the code to a new function and call this function
only once during intel_fbc_choose_crtc() instead of once per plane.
Those checks are independent from planes/CRTCs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 14 --
1 file changed, 12
Em Sex, 2016-11-11 às 20:51 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 11, 2016 at 02:57:40PM -0200, Paulo Zanoni wrote:
> >
> > Ville pointed out that intel_fbc_choose_crtc() is iterating over
> > all
> > planes instead of just the primary planes. There are no re
Em Sex, 2016-11-11 às 21:13 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 11, 2016 at 05:01:54PM -0200, Paulo Zanoni wrote:
> >
> > Em Sex, 2016-11-11 às 20:51 +0200, Ville Syrjälä escreveu:
> > >
> > > On Fri, Nov 11, 2016 at 02:57:40PM -0200, Paulo Zanoni wrote
Em Sex, 2016-11-11 às 22:24 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 11, 2016 at 05:57:28PM -0200, Paulo Zanoni wrote:
> >
> > Em Sex, 2016-11-11 às 21:13 +0200, Ville Syrjälä escreveu:
> > >
> > > On Fri, Nov 11, 2016 at 05:01:54PM -0200, Paulo Zanoni wrote:
Em Ter, 2016-11-08 às 17:38 -0800, Matt Roper escreveu:
> On Tue, Nov 08, 2016 at 06:22:11PM -0200, Paulo Zanoni wrote:
> >
> > The previous spec version said "double Ytile planes minimum lines",
> > and I interpreted this as referring to what the spec calls "
Em Sex, 2016-11-11 às 14:57 -0200, Paulo Zanoni escreveu:
> Ville pointed out two ugly defects in the FBC code, and while trying
> to fix them I spotted a few extra things. No real-world bugs fixed
> here, but IMHO the code is much easier to read now.
I merged patches 1-5 and 7, and wi
lane in order to assign its score
instead of looking at every primary plane on the same commit.
We still only set scores of 0 and 1 and we don't really do the
score-checking loop.
Cc: Ville Syrjälä
Reported-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c |
Em Seg, 2016-11-14 às 22:26 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 11, 2016 at 06:49:59PM -0200, Paulo Zanoni wrote:
> >
> > Em Sex, 2016-11-11 às 22:24 +0200, Ville Syrjälä escreveu:
> > >
> > > On Fri, Nov 11, 2016 at 05:57:28PM -0200, Paulo Zanoni wrote:
Em Qua, 2016-11-16 às 12:13 +0200, Jani Nikula escreveu:
> We no longer cater for pre-production revisions of Skylake.
Reviewed-by: Paulo Zanoni
>
> Fixes: d4362225e8cb ("drm/i915/gvt: update misc ctl regs base on
> stepping info")
> Cc: Ping Gao
> Cc: Zheny
Em Qui, 2016-11-10 às 11:24 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
>
(removed a bunch of stuff here)
> >
> > >
> >
> >
> > >
> > > + bool y_tile_enabled = false;
> > > +
> > if (!platforms_that_require_the_wa) {
> > wa = WATERMARK_WA_NONE;
> > return;
> > }
> this function is not
way to reproduce the problem, and tell us.
- Boot with drm.debug=0xe, reproduce the problem, then send us the
dmesg file.
v2: Don't enable by default on SKL.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
ix this in the Kernel we
may revert this commit.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 9090a74..4d40e24 100644
-
cific features and in the frontbuffer
tracking subsystem.
We're not checking sink CRCs since they're still unreliable and we
don't want false negatives in the CI.
It takes 5 seconds to run this test on my machines.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbu
please see:
commit a98ee79317b4091cafb502b4ffdbbbe1335e298c
Author: Paulo Zanoni
Date: Tue Feb 16 18:47:21 2016 -0200
drm/i915/fbc: enable FBC by default on HSW and BDW
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+),
racking: be aware of the new FBC Kernel workaround
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_gem.c | 18 --
drivers/gpu/drm/i915/intel_drv.h
orever. In order to avoid this, keep it simple and
just recreate the FBs at every subtest.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/tests/kms_frontbuffer_tracking
Let's be good citizens and properly handle our garbage.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 26e12d0..0ea1dde 100644
--- a/
While PSR has problems with GTT mmaps, we're studying the possibility
of implementing a workaround for FBC that affects CPU and WC mmaps. So
prefer the BLT method since it behaves the same with both features.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 6 +++---
1
ound, then this
commit is going to break a lot of tests. The Kernel commit you need
is:
drm/i915: opt-out CPU and WC mmaps from FBC
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 24
1 file changed, 24 insertions(+)
diff --g
, and we
would still be helpless when testing the combination of FBC+PSR.
Also notice that we still hardcode pipe A for the primary connector,
regardless of whether it supports it. This will be solved in the next
commits.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c
Move it from pm_rpm.c to lib/igt_kms and remove the hardcoded version
from kms_frontbuffer_tracking. I'm also planning to add other callers.
Signed-off-by: Paulo Zanoni
---
lib/igt_kms.c| 18 ++
lib/igt_kms.h| 1 +
All the tests I wrote always assumed that every connector supported
CRTC 0. This is not the case for BSW and possibly others, so fix the
tests before the CI reports more failures.
Signed-off-by: Paulo Zanoni
---
lib/igt_kms.c| 32
lib
We already pass the crtc id, so use the id to retrieve the index.
We'll change the way we pass the crtc id in the next commits, so we'll
have to call a function to calculate the index based on the id at that
point. Do the change now in order to avoid big commits later.
Signed-off-by: Pa
We're going to make our search for connnectors a little more
complicated, so extract the function since we're going to call it a
few more times.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 70 ++--
1 file changed, 38 inserti
to the the ggtt but all aliased ppgtt views of the framebuffer.
> By
> moving the critical section to the object and only doing so for
> framebuffer writes we can reduce the tracking even further by only
> watching framebuffers and not vma.
That fixes the test failures I was seeing. Thank
l
> debug messages which happen immediately before calling
> skl_update_scaler. This way we get rid of the sole debug
> message when switching virtual terminals for example.
I also got annoyed by this at some point.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Tvrtko Ursul
really like the fact that we unified plane/id/i into just
plane_id.
In general, I dislike the fact that many new lines go past 80 columns
now :).
A few comments follow:
>
> Cc: Matt Roper
> Cc: Paulo Zanoni
> Cc: Maarten Lankhorst
> Cc: Lyude
> Signed-off-by: Ville
IMARY,
> + PLANE_SPRITE0,
> + PLANE_SPRITE1,
> + PLANE_CURSOR,
> + I915_MAX_PLANES,
> +};
We now have two different enums defining PLANE_SOMETHING, and we even
moved some stuff from one to the other. I think this adds more
confusion to the code, so we would probably be
ANES;
> (__p)++) \
> + for_each_if ((__crtc)->plane_ids_mask & (1 <<
> (__p)))
> +
Let's be consistent: either use BIT() everywhere or use (1 << bit)
everywhere :).
Reviewed-by: Paulo Zanoni .
> enum port {
> PORT_NONE = -1,
>
uot; code virtually
> identical, so the next logical step would likely be dropping one
> of the copies.
Something something 80 columns something something. Also, this will
need a rebase, but the idea is sane, so with a bug-free rebase:
Reviewed-by: Paulo Zanoni .
>
> Signed-off-by: Vill
_DISPLAY_BASE + 0x6d918 +
> (sprite) * 0x1000)
> -#define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE +
> 0x6d91c + (sprite) * 0x1000)
> +#define SPCSCC01(plane) _MMIO_CHV_SPCSC(plane,
> 0x6d90c)
> +#define SPCSCC23(plane) _MMIO_CHV_SPCSC(plane,
>
agnostic (for now) and start indexing sprites from 0 we'll add a
> small
> helper to convert between the two bases.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 73 ---
> --
> 1
Em Ter, 2016-11-08 às 16:47 +0200, ville.syrj...@linux.intel.com
escreveu:
> From: Ville Syrjälä
>
> Let's try not to abuse plane->plane for sprites on VLV/CHV and
> instead
> use plane->id. Since out watermark structures aren't entirely plane
> type
> agnostic (for now) and start indexing sprite
Em Qui, 2016-11-17 às 21:43 +0200, Ville Syrjälä escreveu:
> On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> >
> > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrj...@linux.intel.com
> > escreveu:
> > >
> > > From: Ville Syrjälä
> > >
Em Ter, 2016-11-08 às 16:47 +0200, ville.syrj...@linux.intel.com
escreveu:
> From: Ville Syrjälä
>
> Now we've rename the local plane id variable as 'plane_id' everywhere
> except the pre-SKL primary plane code. Let's do the rename there as
> well
> so that we'll free up the name 'plane' for use
Em Sex, 2016-11-18 às 16:32 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 18, 2016 at 12:17:06PM -0200, Paulo Zanoni wrote:
> >
> > Em Qui, 2016-11-17 às 21:43 +0200, Ville Syrjälä escreveu:
> > >
> > > On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
Em Sex, 2016-11-18 às 16:34 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 18, 2016 at 12:25:30PM -0200, Paulo Zanoni wrote:
> >
> > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrj...@linux.intel.com
> > escreveu:
> > >
> > > From: Ville Syrjälä
> >
te-
> >base.visible) {
> *enabled = false;
> return 0;
> }
>
> - if (apply_memory_bw_wa && fb->modifier ==
> I915_FORMAT_MOD_X_TILED)
> + y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> + fb->
= DIV_ROUND_UP(8 * cstate-
> >base.adjusted_mode.crtc_htotal *
> + 1000, pixel_rate);
Weird indentation here again. Is your editor configured to show tabs as
4 spaces?
> + if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
Once we
latency += 4;
> +
Nitpick: put this a little below so it's next to the other code that
changes the latency.
With or without this:
Reviewed-by: Paulo Zanoni
> y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> f
Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> This patch adds IPC support for platforms. This patch enables IPC
> only for BXT/KBL platform as for SKL recommendation is to keep is
> disabled.
> IPC (Isochronous Priority Control) is the hardware feature, which
> dynamically controles t
Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> This patch Adds a function to extract intel_crtc_state from the
> atomic_state, if not available it returns NULL.
Reviewed-by: Paulo Zanoni
> Signed-off-by: Mahesh Kumar
> ---
> drivers/gpu/drm/i915/i
Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> This patch changes Watermak calculation to fixed point calculation.
> Problem with current calculation is during plane_blocks_per_line
> calculation we divide intermediate blocks with min_scanlines and
> takes floor of the result because o
Em Ter, 2016-11-22 às 19:05 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
> On Tuesday 22 November 2016 12:16 AM, Paulo Zanoni wrote:
> >
> > Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> > >
> > > This patch adds IPC support for platforms. Thi
5/brw_wm_surface_state.c | 3 +-
> src/mesa/drivers/dri/i965/intel_fbo.c| 17 +-
> src/mesa/drivers/dri/i965/intel_image.h | 5 +
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 139 +++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h|
Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu:
> This series implements following set of functionality
> Implement IPC WA's for Broxton/KBL
> Enable IPC in supported platforms
> Convert WM calculation to fixed point calculation
> Calculation of System memory Bandw
Em Qua, 2016-12-07 às 13:58 +, Chris Wilson escreveu:
> More changes to GEM are on the cards, so before touching it again,
> let's
> try and nail down how the internals are meant to work. The advantage
> of mock testing is that we can write a universal test independent of
> the
> hw (e.g. testi
Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu:
> This patch adds support to decode system memory bandwidth
> which will be used for arbitrated display memory percentage
> calculation in GEN9 based system.
>
> Changes from v1:
> - Address comments from Paulo
> - implement decode functi
Em Ter, 2016-12-13 às 21:17 +0200, Ville Syrjälä escreveu:
> On Tue, Dec 13, 2016 at 11:00:50AM -0800, Linus Torvalds wrote:
> >
> > This isn't new, but I thought I'd report it since it doesn't seem
> > to
> > get fixed on its own..
For me this is new. Ever since September, my SKL SDP booted 100%
BSpec got updated and this workaround is now listed as standard
required programming for all subsequent projects.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
is to ask everybody with screen flickering problems to
test this patch. Hopefully we'll be able to add a bunch of Bugzilla
tags here before merging it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94605
Cc: sta...@vger.kernel.org
Signed-off-by: Paulo Zanoni
---
drivers/gp
Em Ter, 2016-12-13 às 17:57 -0200, Paulo Zanoni escreveu:
> BSpec got updated and this workaround is now listed as standard
> required programming for all subsequent projects.
>
Cc: sta...@vger.kernel.org
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i91
org/show_bug.cgi?id=96704
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96569
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95176
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94985
Cc: # v4.6+
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Paulo Zanoni
---
drivers/gpu/
Em Qua, 2016-12-14 às 08:00 +, Argotti, Yann escreveu:
> >
> >
> > Acked-by: Rodrigo Vivi
> > Reviewed-by: Rodrigo Vivi
> >
> >
> >
> > On Tue, 2016-12-13 at 18:57 -0200, Paulo Zanoni wrote:
> > >
> > > We'
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