vblank
before enabling and before disabling FBC.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16ed44bfd734
vblank
before enabling and before disabling FBC.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16ed44bfd734
vblank
before enabling and before disabling FBC.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16ed44bfd734
device, only by writing 1 to clear
sticky bit 0 in DPCD 0x2006 in sink is mentioned.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915
out reboot).
Tested this patch and works fine on Gen9 Intel chromebook, PSR2 was
enabled back in next iteration, no other sideeffects observed.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gp
ose, Souza)
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 16e9ff47d519..1037b716c1c0 100644
--- a/drivers/gp
alue needs to be corrected in TCON of the panel
since this value comes from DPCD reg 0x2009 offset and i915 driver
uses it. Working with AUO panel vendor to get this fixed in the
panel TCON. In the meantime fixing this as DPCD quirk in the kernel.
Signed-off-by: Gaurav K Singh
---
drivers/gpu
software,
after drawing line, line delay was observed.Also can see flash, garbage
and even shaking display sometimes.
With this fix, issues reported were resolved on Gen9 and Gen11 Intel
chromebooks.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 2 +-
1 file
software,
after drawing line, line delay was observed.Also can see flash, garbage
and even shaking display sometimes.
With this fix, issues reported were resolved on Gen9 and Gen11 Intel
chromebooks. Tested the patch on non-PSR, PSR1 and PSR2 panels, no issue
observed.
Signed-off-by: Gaurav K Singh
for BXT. Extending this fix to BXT as well.
Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
.
Tested by Du,Wenkai on GLK board.
Bspec: 21829
v2: Instead of checking GEN9_BC, BXT and GLK macros, use IS_GEN9 macro
Signed-off-by: Gaurav K Singh
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
.
Tested by Du,Wenkai on GLK board.
Bspec: 21829
v2: Instead of checking GEN9_BC, BXT and GLK macros, use IS_GEN9 macro (Jani N)
Signed-off-by: Gaurav K Singh
Reviewed-by: Abhay Kumar
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
this fix to BXT as well.
Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.
Bspec: 21829
Signed-off-by: Gaurav K Singh
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
this fix to BXT as well.
Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.
Bspec: 21829
Signed-off-by: Gaurav K Singh
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
this fix to BXT as well.
Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.
Bspec: 21829
Signed-off-by: Gaurav K Singh
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
.
Tested by Du,Wenkai on GLK board.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_audio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 656f6c931341..73b1e0b96f88 100644
--- a
. The PPS contains parameters that
the decoder needs to correctly decode pictures.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 389
1 file changed, 389 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm
.
Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in
few weeks.
Dropping the patches to get the review started.
Gaurav K Singh (10):
drm: i915: Defining Compression Capabilities
drm: i915: Get DSC capability from DP sink
drm: i915: Enable/Disable DSC in DP sink
drm
used at the encoder(@Source)
and decoder(@Sink).
The PPS is not considered to be part of any picture or slice budget
within the DSC coding algorithm. This patch populates PPS parameters
that needs to be transmitted to the Sink device.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915
Below changes are there as part of this patch:
1. Adding Rate Control parameters for DSC
2. Compute Rate Control parameters
3. Compute DSC parameters for Picture Parameter Set
4. Adding a new .c file for VDSC operations
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/Makefile | 1
Sink device once DIP PPS is enabled in DIP
ctrl reg
4. DSC is only enabled only after Gen9 onwards
5. DSC capability should be supported from Sink side before programming
the source side.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_vdsc.c | 425
For Vesa Display Stream compression, defining structures for
compression capabilities to be stored in encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 125 +++
drivers/gpu/drm/i915/intel_drv.h | 62 +++
include
Get decompression capabilities from DP sink by doing
DPCD reads of different offsets as per eDP/DP specs.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 167
1 file changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/i915
during DP encoder enable sequence before sending PPS.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_ddi.c | 4
drivers/gpu/drm/i915/intel_dp.c | 14 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
include/drm/drm_dp_helper.h | 2 ++
4 files changed, 22 insertions
1. Send PPS and enable DSC after decompression is enabled in DP sink
2. Enable DSC in Source before enabling pipe
3. Disabling compression after disabling pipe, but before disabling port
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_vdsc.c | 51 +++
2
Defining all mmio regs from Gen9 onwards to be used
for VDSC programming.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 58 ++
drivers/gpu/drm/i915/i915_reg.h | 448
2 files changed, 506 insertions(+)
diff --git a/drivers/gpu
this fix to BXT as well.
Bspec: 21829
Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.
v2:
* Mention Bspec Index in commit message(Dhinakaran Pandiyan)
Signed-off-by: Gaurav K Singh
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1
On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh
---
Depending on the correct refclk, n ,p for CHT, calculate
the dsi clk during readout DSI HW state.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b
This patch is in preparation for the DSI dual link
port enable and disable related changes.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file changed, 32 insertions(+), 11 deletions(-)
diff
For dual link MIPI Panels, few packets needs to be sent to Port A or
Port C or both. Based on the port no from MIPI Sequence Block#53, these
sequences needs to be sent accordingly.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.h |1
_PORT macro to be used instead of _TRANSCODER macro for all MIPI DSI regs.
New macro added for mapping the pipe to MIPI Ports.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h |4 ++
drivers/gpu/drm/i915/i915_reg.h | 98 +++
2 files
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 68
IPI for #define variables
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |8
drivers/gpu/drm/i915/intel_ds
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 255
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c |9 ++---
1 file
loop.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 9cf
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h
the second version of patches.
Regards
Gaurav
Gaurav K Singh (11):
drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
reg
drm/i915: MIPI Sequence to be sent to the DSI Controller based on the
port no from VBT
drm/i915: Cleanup in i915_reg.h for all MIPI
All macros of MIPI regs now uses port no instead of pipe no.Based on the
pipe, port no is determined and used to read or write MIPI regs during
enabling & disbling MIPI encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c |
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e900f01..a2bb321 100644
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c |9 ++---
1 file
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the portno from MIPI Sequence Block#53, these sequences needs to be
sent accordingly.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915
the second version of patches.
v3: for_each_dsi_port macro used instead of for loop for dual link support
Regards
Gaurav
Gaurav K Singh (9):
drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
reg
drm/i915: Added port as parameter to the functions which does
This patch is in preparation for the DSI dual link
port enable and disable related changes.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file changed, 32 insertions(+), 11 deletions(-)
diff
IPI for #define variables
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |8
drivers/gpu/drm/i915/intel_ds
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.
v2: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/dri
Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
IPI for #define variables
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |8
drivers/gpu/drm/i915/intel_dsi.h |6 ++
drivers/
This patch is in preparation for the DSI dual link
port enable and disable related changes.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file changed, 32 insertions(+), 11 deletions(-)
diff
for dual link configuration
check
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_dsi.c | 37 +++-
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/dri
the second version of patches.
v3: for_each_dsi_port macro used instead of for loop for dual link support
v4: From 6th patch, separte patch created for DSI Pll lock check. All review
comments of Jani, Nikula have been addressed.
Regards
Gaurav
Gaurav K Singh (10):
drm/i915: New functions added
-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e18abd..22b1570 100644
properly
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 75
drivers/gpu/drm/i915/intel_dsi_cmd.h | 46 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 25 ++
3 files changed, 74 insertions(+), 72
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
v3: separate patch created for cck read for checking PLL to be locked
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
for dual link configuration
check
v4: Masking of the required MIPI port bits before writing proper values
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_dsi.c |
IPI for #define variables
v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
drivers/gpu/
Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.
v2: dpio_lock unlocked now in case DSI PLL lock fails
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c |6 --
1 file changed
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
v4: Added comments for the usage of AFE latchout bit
Signed-off-by: Gaurav K Singh
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
v4: Renamed mode_hactive variable to mode_hdisplay
Signed-off-by: Gaurav K Singh
Signed
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
v4: Renamed mode_hactive variable to mode_hdisplay
Signed-off-by: Gaurav K Singh
Signed
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable DSI on Port C. These patches have been tested on a 1920 x 1200 panel
on Port C.
Regards
Gaurav
Gaurav K Singh (4):
drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C
drm/i915: DSI sequence related
DSI Pll1 is used for enabling DSI on Port C.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..74a6fb5 100644
Due to some hardware limitations, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with Pipe B.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 21
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |9 -
1 file changed, 8 insert
Common bit to be used for both DSI Port A & DSI Port C.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8f8b952..215
DSI Pll1 is used for enabling DSI on Port C.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..9b7f6a5
DSI Pll1 is used for enabling DSI on Port C.
v2: Addressed review comments of Jani
- Used & operator instead of == for intel_dsi->ports
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/
this software workaround for BYT
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 215d004..42b6d6f 100644
For CHT changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh
---
gned-off-by: Gaurav K Singh
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269..5493aef 10
Signed-off-by: Gaurav K Singh
---
tools/intel_bios.h| 26 +
tools/intel_bios_reader.c | 272 +
2 files changed, 298 insertions(+)
diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 752379a..aedc5fc 100644
--- a/tools
Signed-off-by: Gaurav K Singh
---
tools/intel_bios.h| 132 +
tools/intel_bios_reader.c | 94
2 files changed, 226 insertions(+)
diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 832c580..752379a
next enable sequence causing
display blank out.
v2: Use drm_blank_off instead of platform specific disable vblank functions
(Daniel)
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 14 ++
1 file changed, 14 insertions(+)
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu
Allocate gem memory for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
v2: lock mutex before gem object unreference and later set gem obj ptr to NULL
(Gaurav)
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit
Hi,
These patches enable DSI dual link mode on BXT boards. These set of patches
build on top of the floated DSI Video mode patches on BXT (Uma's patches).
Regards
Gaurav
Gaurav K Singh (4):
drm/i915: Enable dual link mode in BXT
drm/i915: Use adjusted mode clk for calculating DSI clk
Before setting the MIPI device to ready state, execute the RESET
sequence.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c |2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 15 +++
include/drm/drm_panel.h|9 +
3
Program the required mmio regs for hactive and vactive display size.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
Earlier, pclk was getting used for calculating DSI clk. For single link
MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
halved, DSI clk will have a wrong value.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |4 +++-
1 file changed, 3
Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.
Signed-off-by: Deepak M
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h |7 ---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu
mode set and no frames
are sent.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/intel_display.c | 47 ++
drivers/gpu/drm/i915/intel_drv.h |6 +
2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm
For command mode and video mode, panel prepare, wait for FIFO
checks are required. Making these changes generic across command
mode and video mode.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 10
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu
next enable sequence causing
display blank out.
v2: Use drm_blank_off instead of platform specific disable vblank functions
(Daniel)
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 15 +++
1 file changed, 15 insertions(+)
The bpp value which is used while calulating the txbyteclkhs values
should be wrt the pixel format value. Currently bpp is coming
from pipe config to calculate txbyteclkhs.
Signed-off-by: Deepak M
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/intel_dsi.c |5 ++---
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers
Reset the display hardware if video mode to command mode transition
has to be done in MIPI display. otherwise command mode will not work.
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c
While enabling MIPI Port in command mode, enable tearing effect
by GPIO pin.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers
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