During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dd518d6..c53f66d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2158,6 +2158,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
return;
}
+ if (crtc->config->dsi_self_refresh) {
+ val = val | PIPECONF_MIPI_DSR_ENABLE;
+ I915_WRITE(reg, val);
+ }
+
I915_WRITE(reg, val | PIPECONF_ENABLE);
POSTING_READ(reg);
}
--
1.7.9.5
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