== Series Details ==
Series: drm/i915/tbt: Add CFGCR0/1 registers for TBT
URL : https://patchwork.freedesktop.org/series/49677/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4820_full -> Patchwork_10182_full =
== Summary - WARNING ==
Minor unknown changes coming with Pat
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations
== Series Details ==
Series: drm/i915: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/49663/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4822 -> Patchwork_10185 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10
From: Madhav Chauhan
This patch calculate various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.
v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
v3: Rebase
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
driv
From: Madhav Chauhan
In Gen11, DPLL 0 and 1 are shared between DDI and DSI.
Most of the steps for enabling DPLL are common across DDI
and DSI. This patch makes icl_dpll_enable() generic which
will be used by all the encoders.
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
d
== Series Details ==
Series: drm/i915/psr: Enable AUX-A IO power well on ICL for PSR
URL : https://patchwork.freedesktop.org/series/49682/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4822_full -> Patchwork_10184_full =
== Summary - SUCCESS ==
No regressions found.
/commits/Ville-Syrjala/drm-nouveau-Disable-atomic-support-on-a-per-device-basis/20180914-111059
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations
Hi,
just a ping for review :)
-Mahesh
On 9/8/2018 11:40 AM, Mahesh Kumar wrote:
This cleanup patch makes changes to use for_each_pipe loop
during bit-mask assignment of allowed crtc with encoder.
changes:
- use BIT(i) macro instead of (1 << i) (Chris)
changes from V2:
- use int for consist
On 9/12/2018 6:25 AM, Manasi Navare wrote:
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compresse
The prior assumption was that we did not need to reset the CSB on
wedging when cancelling the outstanding requests as it would be cleaned
up in the subsequent reset prior to restarting the GPU. However, what
was not accounted for was that in performing the reset, we would try to
process the outstan
Gen11/ICL DSI has to choose one of the free available DPLL which can also be
tied to DDI A/B combo phy ports. In legacy platforms that was not the case as
DSI had separate/exclusive PLLs.
ICL DPLL enable/disable steps are 80% common if DPLL is tied to DDI interface
(HDMI/DP) or DSI. If DSI impleme
From: Madhav Chauhan
This patch implements steps specific to DSI for
enabling PLL.
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/dri
If we try and fail to allocate a i915_request, we apply some
backpressure on the clients to throttle the memory allocations coming
from i915.ko. Currently, we wait until completely idle, but this is far
too heavy and leads to some situations where the only escape is to
declare a client hung and res
Quoting Tvrtko Ursulin (2018-09-14 09:14:54)
>
> On 13/09/2018 20:33, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index d7fcbba8e982..7b1f322f232b 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/
Quoting José Roberto de Souza (2018-09-13 23:13:41)
> All DRM_CLIENT capabilities are tied to KMS support, so returning
> -ENOTSUPP when KMS is not supported.
The posix errno is ENOTSUP (ENOTSUPP is internal). Now since we have no
ENOTSUP in the uapi, I've switched to using EOPNOTSUP as that is
do
On Thu, Sep 13, 2018 at 11:02 PM, Lyude Paul wrote:
> Hm, one nitpick here. Since /sys/kernel/debug/dri/*/state creation depends on
> the driver supporting atomic, maybe it would be good to make it so that we set
> DRIVER_ATOMIC in the driver_stub structure, then disable it per-device
> depending
On 13/09/2018 20:33, Chris Wilson wrote:
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at dete
On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder re
== Series Details ==
Series: drm/i915: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/49663/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4822_full -> Patchwork_10185_full =
== Summary - WARNING ==
Minor unknown changes coming with Pa
Once we have flushed the first request through the system to both load a
context and record the default state; tell the GPU to park and idle
itself, putting itself immediately (hopefully at least) into a
powersaving state, and allowing ourselves to start from known state
after setting up all our bo
In order to reduce latency when checking for idle we kick the tasklet
directly. Sometimes this is not enough as it is queued on another cpu
and so to improve the accuracy of this idle-check (and so to reduce
latency overall by avoiding another pass, or worse declaring a timeout!)
wait for the taskl
On 14/09/2018 09:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 09:14:54)
On 13/09/2018 20:33, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d7fcbba8e982..7b1f322f232b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/
On Wed, Sep 12, 2018 at 10:33:06AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> igt_skip_on_simulation is called both directly from tests but also from
> library helpers. In the latter case especially the logged caller name is
> useless since it is always the helper itself. What we ins
Quoting Tvrtko Ursulin (2018-09-14 10:12:15)
>
> On 14/09/2018 09:21, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-14 09:14:54)
> >>
> >> On 13/09/2018 20:33, Chris Wilson wrote:
> >>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> >>> b/drivers/gpu/drm/i915/intel_lrc.c
> >>> index d7
On 14/09/2018 10:12, Daniel Vetter wrote:
On Wed, Sep 12, 2018 at 10:33:06AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
igt_skip_on_simulation is called both directly from tests but also from
library helpers. In the latter case especially the logged caller name is
useless since it is a
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++
1 file changed, 11
On 14/09/2018 10:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 10:12:15)
On 14/09/2018 09:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 09:14:54)
On 13/09/2018 20:33, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lr
== Series Details ==
Series: Enable ICL DSI PLL
URL : https://patchwork.freedesktop.org/series/49683/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_dpll_mgr.o
drivers/gpu/drm/i915/int
On 14/09/2018 09:34, Chris Wilson wrote:
Once we have flushed the first request through the system to both load a
context and record the default state; tell the GPU to park and idle
itself, putting itself immediately (hopefully at least) into a
powersaving state, and allowing ourselves to start
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++
1 file changed, 11
Now that we reload both RING_HEAD and RING_TAIL when rebinding the
context, we do not need to scrub those registers immediately on resume.
v2: Handle the perma-pinned contexts.
v3: Set RING_TAIL on context-pin so that we always have known state in
the context image for the ring registers and all p
Once we have flushed the first request through the system to both load a
context and record the default state; tell the GPU to park and idle
itself, putting itself immediately (hopefully at least) into a
powersaving state, and allowing ourselves to start from known state
after setting up all our bo
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.
v2: With extra enthusiasm
On 14/09/2018 10:21, Chris Wilson wrote:
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i9
On Fri, Sep 14, 2018 at 10:19:29AM +0100, Tvrtko Ursulin wrote:
>
> On 14/09/2018 10:12, Daniel Vetter wrote:
> > On Wed, Sep 12, 2018 at 10:33:06AM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > igt_skip_on_simulation is called both directly from tests but also from
> > > l
Quoting Tvrtko Ursulin (2018-09-14 10:40:43)
>
> On 14/09/2018 09:34, Chris Wilson wrote:
> > Once we have flushed the first request through the system to both load a
> > context and record the default state; tell the GPU to park and idle
> > itself, putting itself immediately (hopefully at least)
Quoting Daniel Vetter (2018-09-14 10:46:25)
> On Fri, Sep 14, 2018 at 10:19:29AM +0100, Tvrtko Ursulin wrote:
> >
> > On 14/09/2018 10:12, Daniel Vetter wrote:
> > > On Wed, Sep 12, 2018 at 10:33:06AM +0100, Tvrtko Ursulin wrote:
> > > > From: Tvrtko Ursulin
> > > >
> > > > igt_skip_on_simulatio
Quoting Tvrtko Ursulin (2018-09-14 10:43:12)
>
> On 14/09/2018 10:21, Chris Wilson wrote:
> > Check we can indeed acquire a WB mapping of the context image on module
> > load. Later this will give us the opportunity to validate that we can
> > switch from WC to WB as required.
> >
> > Signed-off-
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit the backpressure for
i915_request allocation
URL : https://patchwork.freedesktop.org/series/49688/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4823 -> Patchwork_10187 =
== Summary - SUCCESS ==
No
On 14/09/2018 10:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 10:40:43)
On 14/09/2018 09:34, Chris Wilson wrote:
Once we have flushed the first request through the system to both load a
context and record the default state; tell the GPU to park and idle
itself, putting itself im
On 14/09/2018 10:51, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 10:43:12)
On 14/09/2018 10:21, Chris Wilson wrote:
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as
On 14/09/2018 09:00, Chris Wilson wrote:
If we try and fail to allocate a i915_request, we apply some
backpressure on the clients to throttle the memory allocations coming
from i915.ko. Currently, we wait until completely idle, but this is far
too heavy and leads to some situations where the onl
On 14/09/2018 09:00, Chris Wilson wrote:
In order to reduce latency when checking for idle we kick the tasklet
directly. Sometimes this is not enough as it is queued on another cpu
and so to improve the accuracy of this idle-check (and so to reduce
latency overall by avoiding another pass, or wo
Quoting Tvrtko Ursulin (2018-09-14 11:03:18)
>
> On 14/09/2018 10:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-14 10:43:12)
> >>
> >> On 14/09/2018 10:21, Chris Wilson wrote:
> >>> Check we can indeed acquire a WB mapping of the context image on module
> >>> load. Later this will gi
Quoting Tvrtko Ursulin (2018-09-14 11:03:03)
>
> On 14/09/2018 10:47, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-14 10:40:43)
> >>
> >> On 14/09/2018 09:34, Chris Wilson wrote:
> >>> Once we have flushed the first request through the system to both load a
> >>> context and record the
== Series Details ==
Series: drm/i915: Park the GPU on module load
URL : https://patchwork.freedesktop.org/series/49693/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4824 -> Patchwork_10188 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10188 ab
On Tue, Sep 11, 2018 at 05:56:01PM -0700, Manasi Navare wrote:
> On Icelake, a separate power well PG2 is created for
> VDSC engine used for eDP/MIPI DSI. This patch adds a new
> display power domain for Power well 2.
>
> Cc: Rodrigo Vivi
> Cc: Imre Deak
> Signed-off-by: Manasi Navare
> ---
>
Quoting Chris Wilson (2018-09-14 10:47:36)
> Quoting Tvrtko Ursulin (2018-09-14 10:40:43)
> >
> > On 14/09/2018 09:34, Chris Wilson wrote:
> > > Once we have flushed the first request through the system to both load a
> > > context and record the default state; tell the GPU to park and idle
> > >
On 14/09/2018 11:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 11:03:18)
On 14/09/2018 10:51, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-14 10:43:12)
On 14/09/2018 10:21, Chris Wilson wrote:
Check we can indeed acquire a WB mapping of the context image on module
load.
On 14/09/2018 10:42, Chris Wilson wrote:
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i9
== Series Details ==
Series: drm/i915: Check engine->default_state mapping on module load
URL : https://patchwork.freedesktop.org/series/49694/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4824 -> Patchwork_10189 =
== Summary - SUCCESS ==
No regressions found.
Extern
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit the backpressure for
i915_request allocation
URL : https://patchwork.freedesktop.org/series/49688/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4823_full -> Patchwork_10187_full =
== Summary - SUCCESS
Quoting Tvrtko Ursulin (2018-09-14 11:21:07)
>
> On 14/09/2018 09:00, Chris Wilson wrote:
> > In order to reduce latency when checking for idle we kick the tasklet
> > directly. Sometimes this is not enough as it is queued on another cpu
> > and so to improve the accuracy of this idle-check (and s
On Thu, Sep 13, 2018 at 02:22:48PM -0700, José Roberto de Souza wrote:
> Instead of have the same code spread into 4 platforms lets share it.
> BXT do not have a PCH so here also handling this case by unseting
> RESET_PCH_HANDSHAKE_ENABLE.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers
On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> > On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> >> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> >>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >
== Series Details ==
Series: series starting with [1/4] drm/i915/execlists: Delay updating ring
register state after resume
URL : https://patchwork.freedesktop.org/series/49697/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Delay updating ring register
Now that we reload both RING_HEAD and RING_TAIL when rebinding the
context, we do not need to scrub those registers immediately on resume.
v2: Handle the perma-pinned contexts.
v3: Set RING_TAIL on context-pin so that we always have known state in
the context image for the ring registers and all p
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.
v2: With extra enthusiasm
On Sat, Sep 08, 2018 at 11:40:48AM +0530, Mahesh Kumar wrote:
> This cleanup patch makes changes to use for_each_pipe loop
> during bit-mask assignment of allowed crtc with encoder.
>
> changes:
> - use BIT(i) macro instead of (1 << i) (Chris)
> changes from V2:
> - use int for consistency (Jani
If an asynchronous wait on a foriegn fence, we print a warning
indicating which fence was not signaled. As i915_sw_fences become more
common, include the debug hint (the symbol-name of the target) to help
identify the waiter. E.g.
[ 31.968144] Asynchronous wait on fence sw_sync:gem_eio:1 timed o
== Series Details ==
Series: series starting with [1/4] drm/i915/execlists: Delay updating ring
register state after resume
URL : https://patchwork.freedesktop.org/series/49697/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4825 -> Patchwork_10190 =
== Summary - FAILURE ==
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/execlists: Delay updating ring
register state after resume
URL : https://patchwork.freedesktop.org/series/49708/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Delay updating ring regist
On Thu, Sep 13, 2018 at 09:27:25PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-13 21:01:39)
> > From: Ville Syrjälä
> >
> > With gtt remapping plugged in we can simply raise the stride
> > limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
> >
> > No remapping CCS b
== Series Details ==
Series: drm/i915: Check engine->default_state mapping on module load
URL : https://patchwork.freedesktop.org/series/49694/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4824_full -> Patchwork_10189_full =
== Summary - SUCCESS ==
No regressions found.
On Thu, Sep 13, 2018 at 09:19:00PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-13 21:01:37)
> > diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
> > b/drivers/gpu/drm/i915/selftests/i915_vma.c
> > index ffa74290e054..4fc49c27f13c 100644
> > --- a/drivers/gpu/drm/i915/selftest
Quoting Ville Syrjälä (2018-09-14 13:58:15)
> On Thu, Sep 13, 2018 at 09:19:00PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-09-13 21:01:37)
> > > diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
> > > b/drivers/gpu/drm/i915/selftests/i915_vma.c
> > > index ffa74290e054..4fc49
On Fri, Sep 14, 2018 at 10:42:15AM +0100, Chris Wilson wrote:
> That we use a WB mapping for updating the RING_TAIL register inside the
> context image even on !llc machines has been a source of consternation
> for every reader. It appears to work on bsw+, but it may just have been
> that we have b
On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
On Tue, Jul 10, 2018 at 03:10:12PM
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/execlists: Delay updating ring
register state after resume
URL : https://patchwork.freedesktop.org/series/49708/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4825 -> Patchwork_10191 =
== Summary - SUCCESS
Quoting Ville Syrjälä (2018-09-14 14:03:35)
> On Fri, Sep 14, 2018 at 10:42:15AM +0100, Chris Wilson wrote:
> > That we use a WB mapping for updating the RING_TAIL register inside the
> > context image even on !llc machines has been a source of consternation
> > for every reader. It appears to work
On 9/14/2018 6:36 PM, Madhav Chauhan wrote:
On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
On 7/19/2018 9:52 PM, Ville Syrjäl
On Thu, Sep 13, 2018 at 05:18:22PM -0700, Dhinakaran Pandiyan wrote:
> PSR requires AUX IO power well to be enabled. This was already in place
> for CNL, extend this for ICL too. Not enabling the power well results in
> the aux error interrupts when the hardware exits PSR.
>
> Reported-by: Casey G
From: Tvrtko Ursulin
Period mode tries to execute every workload iteration with a given
frequency.
Up to now code used to calculate the relative sleep needed to hit the
required start of the next iteration, but we can do conceptually better
if we use clock_nanosleep in absolute mode and tell it
On Fri, 2018-09-07 at 11:45 +0300, Stanislav Lisovskiy wrote:
> Introduced new XYUV scan-in format for framebuffer and
> added support for it to i915(SkyLake+).
>
> Stanislav Lisovskiy (2):
> drm: Introduce new DRM_FORMAT_XYUV
> drm/i915: Adding YUV444 packed format support for skl+
>
> driv
Check we have sufficient memory to run the tests before getting trapped
in the swap of despair.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107935
Signed-off-by: Chris Wilson
---
tests/gen3_mixed_blits.c | 1 +
tests/gen3_render_linear_blits.c | 1 +
tests/gen3_render_mixed_bl
== Series Details ==
Series: drm/i915: Include fence-hint for timeout warning (rev3)
URL : https://patchwork.freedesktop.org/series/20264/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4825 -> Patchwork_10192 =
== Summary - SUCCESS ==
No regressions found.
External UR
commit 6209c285e7a5e68dbcdf8fd2456c6dd68433806b upstream.
Since Haswell we have no color range indication either in the pipe or
port registers for DP. Instead, there's a separate register for setting
the DP Main Stream Attributes (MSA) directly. The MSA register
definition makes no references to c
On Fri, Sep 14, 2018 at 02:16:12PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-14 14:03:35)
> > On Fri, Sep 14, 2018 at 10:42:15AM +0100, Chris Wilson wrote:
> > > That we use a WB mapping for updating the RING_TAIL register inside the
> > > context image even on !llc machines has b
On Fri, Sep 14, 2018 at 06:57:23PM +0530, Madhav Chauhan wrote:
> On 9/14/2018 6:36 PM, Madhav Chauhan wrote:
> > On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
> >> On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
> >>> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> On Wed, Sep 12,
On Fri, Sep 14, 2018 at 02:35:38PM +0100, Chris Wilson wrote:
> Check we have sufficient memory to run the tests before getting trapped
> in the swap of despair.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107935
> Signed-off-by: Chris Wilson
Looks consistent with the igt_info().
On Fri, Sep 14, 2018 at 01:36:32PM +, Lisovskiy, Stanislav wrote:
> On Fri, 2018-09-07 at 11:45 +0300, Stanislav Lisovskiy wrote:
> > Introduced new XYUV scan-in format for framebuffer and
> > added support for it to i915(SkyLake+).
> >
> > Stanislav Lisovskiy (2):
> > drm: Introduce new DRM
Chris Wilson writes:
> The prior assumption was that we did not need to reset the CSB on
> wedging when cancelling the outstanding requests as it would be cleaned
> up in the subsequent reset prior to restarting the GPU. However, what
> was not accounted for was that in performing the reset, we w
Instead of have the same code spread into 4 platforms lets share it.
BXT do not have a PCH so here also handling this case by unseting
RESET_PCH_HANDSHAKE_ENABLE.
v2(Rodrigo):
- renamed to intel_pch_reset_handshake()
- added comment about why BXT need the bit to be unset
Cc: Rodrigo Vivi
Signed-
IPC was only added in SKL+(actually we don't even enable for SKL due
WA) so without this change, driver was writing to a reserved bit.
Also removing the uncessary dev_priv->ipc_enabled = false; as now
gens without IPC will not have IPC enabled.
v2(Rodrigo):
- moved the new handling of WA #0477 to
Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a dif
On Fri, 2018-09-14 at 16:47 +0300, Ville Syrjälä wrote:
> On Fri, Sep 14, 2018 at 01:36:32PM +, Lisovskiy, Stanislav wrote:
> > On Fri, 2018-09-07 at 11:45 +0300, Stanislav Lisovskiy wrote:
> > > Introduced new XYUV scan-in format for framebuffer and
> > > added support for it to i915(SkyLake+)
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Lisovskiy, Stanislav
> Sent: perjantai 14. syyskuuta 2018 17.31
> To: ville.syrj...@linux.intel.com
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
> Heikkila, Juha-pekka ; d
== Series Details ==
Series: drm/i915: set DP Main Stream Attribute for color range on DDI platforms
(rev3)
URL : https://patchwork.freedesktop.org/series/48145/
State : failure
== Summary ==
Applying: drm/i915: set DP Main Stream Attribute for color range on DDI
platforms
Using index info t
On Fri, 2018-09-14 at 15:34 +0100, Saarinen, Jani wrote:
> Hi,
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf
> > Of Lisovskiy, Stanislav
> > Sent: perjantai 14. syyskuuta 2018 17.31
> > To: ville.syrj...@linux.intel.com
> > Cc:
On Fri, Sep 14, 2018 at 07:18:44AM -0700, José Roberto de Souza wrote:
> Instead of have the same code spread into 4 platforms lets share it.
> BXT do not have a PCH so here also handling this case by unseting
> RESET_PCH_HANDSHAKE_ENABLE.
>
> v2(Rodrigo):
> - renamed to intel_pch_reset_handshake(
On Fri, Sep 14, 2018 at 07:18:45AM -0700, José Roberto de Souza wrote:
> Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> i915_gem_init_hw().
> So making skl_pch_reset_handshake() handle both cases and calling
On Fri, Sep 14, 2018 at 02:49:09PM +, Lisovskiy, Stanislav wrote:
> On Fri, 2018-09-14 at 15:34 +0100, Saarinen, Jani wrote:
> > Hi,
> >
> > > -Original Message-
> > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > > Behalf
> > > Of Lisovskiy, Stanislav
> > >
On Thu, Sep 13, 2018 at 05:02:05PM -0400, Lyude Paul wrote:
> Hm, one nitpick here. Since /sys/kernel/debug/dri/*/state creation depends on
> the driver supporting atomic, maybe it would be good to make it so that we set
> DRIVER_ATOMIC in the driver_stub structure, then disable it per-device
> de
On Fri, Sep 14, 2018 at 10:49:47AM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2018-09-14 10:46:25)
> > On Fri, Sep 14, 2018 at 10:19:29AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 14/09/2018 10:12, Daniel Vetter wrote:
> > > > On Wed, Sep 12, 2018 at 10:33:06AM +0100, Tvrtko Ursulin wro
On Fri, Sep 14, 2018 at 07:18:46AM -0700, José Roberto de Souza wrote:
> IPC was only added in SKL+(actually we don't even enable for SKL due
> WA) so without this change, driver was writing to a reserved bit.
>
> Also removing the uncessary dev_priv->ipc_enabled = false; as now
> gens without IPC
On Fri, Sep 14, 2018 at 05:52:39PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 14, 2018 at 07:18:44AM -0700, José Roberto de Souza wrote:
> > Instead of have the same code spread into 4 platforms lets share it.
> > BXT do not have a PCH so here also handling this case by unseting
> > RESET_PCH_HANDSH
Avoids error with defining conflicting types.
---
configure.ac | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/configure.ac b/configure.ac
index ee588815..fc76e955 100644
--- a/configure.ac
+++ b/configure.ac
@@ -495,10 +495,10 @@ if test "x$_EXT_CHECK" != "xno" -a "x$DRI
On Thu, 13 Sep 2018 20:22:14 +0300
Ville Syrjälä wrote:
> On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> > On Thu, 13 Sep 2018 20:05:54 +0300
> > Ville Syrjälä wrote:
> >
> > > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> > > > On Wed, 12 Sep 2018 17:10:58 +0
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