On Fri, Sep 14, 2018 at 07:18:45AM -0700, José Roberto de Souza wrote:
> Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> i915_gem_init_hw().
> So making skl_pch_reset_handshake() handle both cases and calling
> it for the missing gens in intel_power_domains_init_hw().
> Ivybridge have a different register and bits but with the same
> objective so moving it too.
>
> v2(Rodrigo):
> - handling IVYBRIDGE case inside intel_pch_reset_handshake()
>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 12 ------------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++++++++++---
> 2 files changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 89834ce19acd..b389e084c8c6 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5296,18 +5296,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> - if (HAS_PCH_NOP(dev_priv)) {
> - if (IS_IVYBRIDGE(dev_priv)) {
> - u32 temp = I915_READ(GEN7_MSG_CTL);
> - temp &= ~(WAIT_FOR_PCH_FLR_ACK |
> WAIT_FOR_PCH_RESET_ACK);
> - I915_WRITE(GEN7_MSG_CTL, temp);
> - } else if (INTEL_GEN(dev_priv) >= 7) {
> - u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> - temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> - }
> - }
> -
> intel_gt_workarounds_apply(dev_priv);
>
> i915_gem_init_swizzling(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1bcd0e51fca1..bca1976fdb1d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3241,10 +3241,22 @@ static void icl_mbus_init(struct drm_i915_private
> *dev_priv)
>
> static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
> {
> - u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> + u32 val;
> +
> + if (IS_IVYBRIDGE(dev_priv)) {
> + if (HAS_PCH_NOP(dev_priv)) {
> + val = I915_READ(GEN7_MSG_CTL);
> + val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> + I915_WRITE(GEN7_MSG_CTL, val);
> + }
> +
> + return;
> + }
I'd go with if-else since both sides are pretty much equal.
> +
> + val = I915_READ(HSW_NDE_RSTWRN_OPT);
>
> /* BXT don't have PCH and it requires that this bit is always unset */
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv))
> val |= RESET_PCH_HANDSHAKE_ENABLE;
> else
> val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> @@ -3756,7 +3768,8 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *dev_priv, bool resume)
> mutex_lock(&power_domains->lock);
> vlv_cmnlane_wa(dev_priv);
> mutex_unlock(&power_domains->lock);
> - }
> + } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> + intel_pch_reset_handshake(dev_priv);
>
> /*
> * Keep all power wells enabled for any dependent HW access during
> --
> 2.19.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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