From: Robert Bragg
In earlier iterations of the i915-perf driver we had a number of
callbacks/hooks from other parts of the i915 driver to e.g. notify us
when a legacy context was pinned and these could run asynchronously with
respect to the stream file operations and might also run in atomic
con
From: Robert Bragg
This avoids redundantly passing an (inout) head and tail pointer to
gen7_append_oa_reports() from gen7_oa_read which doesn't need to
reference either itself.
Moving the head/tail reads and writes into gen7_append_oa_reports should
have no functional effect except to avoid some
From: Robert Bragg
This updates the tail pointer race workaround handling to updating the
'aged' pointer before looking to start aging a new one. There's the
possibility that there is already new data available and so we can
immediately start aging a new pointer without having to first wait for a
From: Robert Bragg
Assuming a uniform mask across all slices, this enables userspace to
determine the specific sub slices enabled. This information is required,
for example, to be able to analyse some OA counter reports where the
counter configuration depends on the HW sub slice configuration.
S
From: Robert Bragg
A minor improvement to debugging output
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
i
From: Robert Bragg
An oa_exponent_to_ns() utility and per-gen timebase constants where
recently removed when updating the tail pointer race condition WA, and
this restores those so we can update the _PROP_OA_EXPONENT validation
done in read_properties_unlocked() to not assume we have a 12.5MHz
ti
From: Robert Bragg
This change is pre-emptively aiming to avoid a potential cause of kernel
logging noise in case some condition were to result in us seeing invalid
OA reports.
The workaround for the OA unit's tail pointer race condition is what
avoids the primary known cause of invalid reports
From: Robert Bragg
Enables userspace to determine the number of slices enabled and also
know what specific slices are enabled. This information is required, for
example, to be able to analyse some OA counter reports where the counter
configuration depends on the HW slice configuration.
Signed-of
From: Robert Bragg
There's no need for the driver to keep reading back the head pointer
from hardware since the hardware doesn't update it automatically. This
way we can treat any invalid head pointer value as a software/driver
bug instead of spurious hardware behaviour.
This change is also a sm
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
From: Robert Bragg
If the function for checking whether there is OA buffer data available
(during a poll or blocking read) has false positives then we want to
avoid a situation where the subsequent read() returns EAGAIN (after
a more accurate check) followed by a poll() immediately reporting
the
Hi,
Taking over from Rob for this v5. This series only has the following
changes from v4 :
- patch 9 & 10 : updated number for GETPARAM after rebase
- patch 12 : drain the GPU before reconfiguring the OA unit to work
around a race condition where the CPU & GPU update the context
image at
From: Robert Bragg
There's a HW race condition between OA unit tail pointer register
updates and writes to memory whereby the tail pointer can sometimes get
ahead of what's been written out to the OA buffer so far (in terms of
what's visible to the CPU).
Although this can be observed explicitly
From: Robert Bragg
If I'm going to complain about a back-to-front convention then the least
I can do is not muddle the comment up too.
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Robert Bragg
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop
On 21-04-17 20:14, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Implement proper two stage watermark programming for g4x. As with
> other pre-SKL platforms, the watermark registers aren't double
> buffered on g4x. Hence we must sequence the watermark update
> carefully around pla
On 18/04/2017 21:13, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 05:56:14PM +0100, Tvrtko Ursulin wrote:
+enum drm_i915_gem_engine_class {
+ DRM_I915_ENGINE_CLASS_OTHER = 0,
+ DRM_I915_ENGINE_CLASS_RENDER = 1,
+ DRM_I915_ENGINE_CLASS_COPY = 2,
+ DRM_I915_ENGINE_CLASS_VID
On 19/04/2017 06:22, Kenneth Graunke wrote:
On Tuesday, April 18, 2017 9:56:14 AM PDT Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Engine discovery uAPI allows userspace to probe for engine
configuration and features without needing to maintain the
internal PCI id based database.
I don't unde
On 19.04.2017 13:13, Marta Lofstedt wrote:
> +
> +__attribute__((format(printf, 1, 2)))
> +static void kmsg(const char *format, ...)
> +#define KERN_EMER"<0>"
> +#define KERN_ALERT "<1>"
> +#define KERN_CRIT"<2>"
> +#define KERN_ERR "<3>"
> +#define KERN_WARNING "<4>"
> +#define KERN_
On 18/04/2017 22:10, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 05:56:15PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Building on top of the previous patch which exported the concept
of engine classes and instances, we can also use this instead of
the current awkward engine selection
This patch proposes a RFC design to handle blending of various
framebuffers with different color spaces, using the DRM color
properties.
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/rfc-design-blending.txt | 52 +
1 file changed, 52 insertions(+)
create mod
== Series Details ==
Series: RFC: Design: DRM: Blending pipeline using DRM plane properties
URL : https://patchwork.freedesktop.org/series/23443/
State : success
== Summary ==
Series 23443v1 RFC: Design: DRM: Blending pipeline using DRM plane properties
https://patchwork.freedesktop.org/api/1.
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediat
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediat
== Series Details ==
Series: series starting with [1/2] drm/i915: Calculate ironlake intermediate
watermarks correctly
URL : https://patchwork.freedesktop.org/series/23444/
State : success
== Summary ==
Series 23444v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/serie
On 19/04/2017 10:41, Chris Wilson wrote:
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the s
On Mon, Apr 24, 2017 at 12:17:48AM -0700, Lionel Landwerlin wrote:
> +static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv)
> +{
> + struct i915_gem_context *ctx;
> + int ret;
> +
> + ret = i915_mutex_lock_interruptible(&dev_priv->drm);
> + if (ret)
> +
Display workaround #1139 for Geminilake instructs us to restrict HDMI
to 8 bpc when htotal is greater than 5460. Otherwise, the pipe is unable
to generate a proper signal and is left in a state where corruption is
seen with other modes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100440
On Mon, 2017-04-24 at 13:47 +0300, Ander Conselvan de Oliveira wrote:
> Display workaround #1139 for Geminilake instructs us to restrict HDMI
> to 8 bpc when htotal is greater than 5460. Otherwise, the pipe is unable
> to generate a proper signal and is left in a state where corruption is
> seen wi
On Mon, Apr 24, 2017 at 11:28:32AM +0100, Tvrtko Ursulin wrote:
>
> On 19/04/2017 10:41, Chris Wilson wrote:
> >All the requests at the same priority are executed in FIFO order. They
> >do not need to be stored in the rbtree themselves, as they are a simple
> >list within a level. If we move the r
Regards
Shashank
On 4/24/2017 4:17 PM, Ander Conselvan de Oliveira wrote:
Display workaround #1139 for Geminilake instructs us to restrict HDMI
to 8 bpc when htotal is greater than 5460. Otherwise, the pipe is unable
to generate a proper signal and is left in a state where corruption is
seen w
== Series Details ==
Series: drm/i915/glk: Don't allow 12 bpc when htotal is too big
URL : https://patchwork.freedesktop.org/series/23451/
State : success
== Summary ==
Series 23451v1 drm/i915/glk: Don't allow 12 bpc when htotal is too big
https://patchwork.freedesktop.org/api/1.0/series/23451
On Mon, 24 Apr 2017, Ander Conselvan De Oliveira wrote:
> On Mon, 2017-04-24 at 13:47 +0300, Ander Conselvan de Oliveira wrote:
>> Display workaround #1139 for Geminilake instructs us to restrict HDMI
>> to 8 bpc when htotal is greater than 5460. Otherwise, the pipe is unable
>> to generate a prop
On 19-04-17 17:43, Daniel Vetter wrote:
> On Thu, Apr 13, 2017 at 11:15:37AM +0200, Maarten Lankhorst wrote:
>> This is required to for i915 to convert connector properties to atomic.
>>
>> Changes since v1:
>> - Add docbook info. (danvet)
>> - Change picture_aspect_ratio to enum hdmi_picture_aspec
On Mon, Apr 24, 2017 at 12:07:47PM +0100, Chris Wilson wrote:
> On Mon, Apr 24, 2017 at 11:28:32AM +0100, Tvrtko Ursulin wrote:
> >
> > On 19/04/2017 10:41, Chris Wilson wrote:
> > Sounds attractive! What workloads show the benefit and how much?
>
> The default will show the best, since everythin
Chris Wilson writes:
> We need to keep track of the last location we ask the hw to read up to
> (RING_TAIL) separately from our last write location into the ring, so
> that in the event of a GPU reset we do not tell the HW to proceed into
> a partially written request (which can happen if that re
Chris Wilson writes:
> If we poison the request before we emit commands, it should be easier to
> spot when we execute an uninitialised request.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=100144
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 1
On Mon, Apr 24, 2017 at 03:21:56PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > We need to keep track of the last location we ask the hw to read up to
> > (RING_TAIL) separately from our last write location into the ring, so
> > that in the event of a GPU reset we do not tell the HW t
Chris Wilson writes:
> We only have to prevent the RING_TAIL from catching the RING_HEAD
> cacheline and do not need to enforce a whole cacheline separation, and in
> the process we can remove one branch from the computation.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_ri
On Mon, Apr 24, 2017 at 01:32:03PM +0100, Chris Wilson wrote:
> On Mon, Apr 24, 2017 at 03:21:56PM +0300, Mika Kuoppala wrote:
> > Chris Wilson writes:
> >
> > > We need to keep track of the last location we ask the hw to read up to
> > > (RING_TAIL) separately from our last write location into t
On 24/04/2017 12:07, Chris Wilson wrote:
On Mon, Apr 24, 2017 at 11:28:32AM +0100, Tvrtko Ursulin wrote:
On 19/04/2017 10:41, Chris Wilson wrote:
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list
On Sun, Apr 23, 2017 at 06:11:04PM +0200, Hans de Goede wrote:
> Hi All,
>
> So I recently bought a (second-hand) Bay Trail tablet which has its LCD
> mounted upside-down. As such I've ported Ville Syrjala's patches to deal
> with this to current mainline and I'm hereby posting them upstream
> for
On Mon, Apr 24, 2017 at 03:29:48PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > If we poison the request before we emit commands, it should be easier to
> > spot when we execute an uninitialised request.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=100144
> > Signe
On Mon, Apr 24, 2017 at 03:37:44PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > We only have to prevent the RING_TAIL from catching the RING_HEAD
> > cacheline and do not need to enforce a whole cacheline separation, and in
> > the process we can remove one branch from the computation
Chris Wilson writes:
> Knowing the neighbouring seqno (current on hw, last submitted to hw)
> provide some useful breadcrumbs to the debug log.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 6 --
> 1 file changed, 4 insertio
In some cases we observed that forcewake isn't kept after
resume and then RC6 residency is not constant.
References: HSD#1804921797
Cc: Arkadiusz Hiler
Cc: Michal Winiarski
Cc: Lukasz Fiedorowicz
Signed-off-by: Ewelina Musial
---
tests/pm_rc6_residency.c | 53 +
On 19/04/2017 10:41, Chris Wilson wrote:
Track the latest fence waited upon on each context, and only add a new
asynchronous wait if the new fence is more recent than the recorded
fence for that context. This requires us to filter out unordered
timelines, which are noted by DMA_FENCE_NO_CONTEXT.
On Mon, Apr 24, 2017 at 01:44:53PM +0100, Tvrtko Ursulin wrote:
>
> On 24/04/2017 12:07, Chris Wilson wrote:
> >On Mon, Apr 24, 2017 at 11:28:32AM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 19/04/2017 10:41, Chris Wilson wrote:
> >>>All the requests at the same priority are executed in FIFO order. T
On Mon, Apr 24, 2017 at 09:34:42AM +0200, Maarten Lankhorst wrote:
> On 21-04-17 20:14, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Implement proper two stage watermark programming for g4x. As with
> > other pre-SKL platforms, the watermark registers aren't double
> > buff
On Mon, Apr 24, 2017 at 02:03:25PM +0100, Tvrtko Ursulin wrote:
>
> On 19/04/2017 10:41, Chris Wilson wrote:
> >Track the latest fence waited upon on each context, and only add a new
> >asynchronous wait if the new fence is more recent than the recorded
> >fence for that context. This requires us
On Mon, Apr 24, 2017 at 02:19:54PM +0100, Chris Wilson wrote:
> On Mon, Apr 24, 2017 at 02:03:25PM +0100, Tvrtko Ursulin wrote:
> >
> > On 19/04/2017 10:41, Chris Wilson wrote:
> > >Track the latest fence waited upon on each context, and only add a new
> > >asynchronous wait if the new fence is mo
Thanks Ville,
I have verified that below patch-set fix the CI regression on the Core2 duo,
see bug: https://bugs.freedesktop.org/show_bug.cgi?id=100548
So, if/when this patch-set lands, I assume we could revert the revert of the
"sched/clock: Fix broken stable to unstable transfer": git@841c8c9
Some drivers - like i915 - may not support the system suspend direct
complete optimization due to differences in their runtime and system
suspend sequence. Add a flag that when set resumes the device before
calling the driver's system suspend handlers which effectively disables
the optimization.
N
Since
commit bac2a909a096c9110525c18cbb8ce73c660d5f71
Author: Rafael J. Wysocki
Date: Wed Jan 21 02:17:42 2015 +0100
PCI / PM: Avoid resuming PCI devices during system suspend
PCI devices will default to allowing the system suspend complete
optimization where devices are not woken up duri
On Mon, Apr 24, 2017 at 11:30:28AM +0200, Maarten Lankhorst wrote:
> The watermarks it should calculate against are the old optimal watermarks.
> The currently active crtc watermarks are pure fiction, and are invalid in
> case of a nonblocking modeset, page flip enabling/disabling planes or any
> o
From: Tvrtko Ursulin
Given a log file created via perf with some interesting trace
events enabled, this tool can generate the timeline graph of
requests getting queued, their dependencies resolved, sent to
the GPU for executing and finally completed.
This can be useful when analyzing certain cla
== Series Details ==
Series: series starting with [v2,1/2] PCI / PM: Add needs_resume flag to avoid
suspend complete optimization
URL : https://patchwork.freedesktop.org/series/23454/
State : success
== Summary ==
Series 23454v1 Series without cover letter
https://patchwork.freedesktop.org/ap
On Mon, Apr 24, 2017 at 03:52:25PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Knowing the neighbouring seqno (current on hw, last submitted to hw)
> > provide some useful breadcrumbs to the debug log.
> >
> > Signed-off-by: Chris Wilson
>
> Reviewed-by: Mika Kuoppala
Pushed the
Patches 1-3: Reviewed-by: Harry Wentland
Patch 4: Acked-by: Harry Wentland
Harry
On 2017-04-21 01:51 AM, Dhinakaran Pandiyan wrote:
Changes in this version:
Used connector->atomic_check() to release vcpi slots instead of the
atomic_release() callback.
This series introduces void * type drive
On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
> Cannonlake has same color setup as Geminilake.
> Legacy color load luts doesn't work anymore on Cannonlake+.
Not sure what that means. The legacy 8bpc LUT i no longer there?
The code still depends on that working, and we also still ex
On Thu, Apr 06, 2017 at 12:15:55PM -0700, Rodrigo Vivi wrote:
> As Geminilake scalers Cannonlake also don't need and don't have
> the "high quality" mode programming.
>
> Cc: Ander Conselvan de Oliveira
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> 1 file c
On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni
>
> Gen 10 should use the exact same code as Gen 9, so change the check to
> take this into consideration, and also assume that future platforms
> will run this code.
>
> Also add a MISSING_CASE(), just in case we
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
== Series Details ==
Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev7)
URL : https://patchwork.freedesktop.org/series/20084/
State : failure
== Summary ==
cc1: all warnings being treated as errors
scripts/Makefile.build:294: recipe for target
'drivers/gpu/drm/i915/gvt/scheduler.o' fa
On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote:
> From: Clint Taylor
>
> vswing programming sequence step 2 requires the Loadgen_select bit to
> be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
> lane width. Implemented the change that was marked as FIXME in th
Em Seg, 2017-04-24 às 21:22 +0300, Ville Syrjälä escreveu:
> On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> >
> > From: Paulo Zanoni
> >
> > Gen 10 should use the exact same code as Gen 9, so change the check
> > to
> > take this into consideration, and also assume that future p
On Mon, Apr 24, 2017 at 05:27:42PM +0300, Imre Deak wrote:
> Some drivers - like i915 - may not support the system suspend direct
> complete optimization due to differences in their runtime and system
> suspend sequence. Add a flag that when set resumes the device before
> calling the driver's syst
On Mon, Apr 24, 2017 at 04:10:41PM -0300, Paulo Zanoni wrote:
> Em Seg, 2017-04-24 às 21:22 +0300, Ville Syrjälä escreveu:
> > On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> > >
> > > From: Paulo Zanoni
> > >
> > > Gen 10 should use the exact same code as Gen 9, so change the ch
On Mon, Apr 24, 2017 at 05:27:43PM +0300, Imre Deak wrote:
> Since
>
> commit bac2a909a096c9110525c18cbb8ce73c660d5f71
> Author: Rafael J. Wysocki
> Date: Wed Jan 21 02:17:42 2015 +0100
>
> PCI / PM: Avoid resuming PCI devices during system suspend
This is not the commit you are looking f
On Mon, Apr 24, 2017 at 10:02:30PM +0200, Lukas Wunner wrote:
> On Mon, Apr 24, 2017 at 05:27:42PM +0300, Imre Deak wrote:
> > Some drivers - like i915 - may not support the system suspend direct
> > complete optimization due to differences in their runtime and system
> > suspend sequence. Add a fl
On Monday, April 24, 2017 10:42:42 PM Lukas Wunner wrote:
> On Mon, Apr 24, 2017 at 10:02:30PM +0200, Lukas Wunner wrote:
> > On Mon, Apr 24, 2017 at 05:27:42PM +0300, Imre Deak wrote:
> > > Some drivers - like i915 - may not support the system suspend direct
> > > complete optimization due to diff
On 20/04/17 17:17, Michel Thierry wrote:
Hmm. Interesting. This relies on i915_gem_retire_requests() (i.e.
struct_mutex) to skip replaying innocent requests, but here we should be
asserting that we do have the hung request.
i.e.
request = i915_gem_find_active_request(engine);
if (!request)
Link to FDO regression list:
https://bugs.freedesktop.org/buglist.cgi?bug_status=NEW&bug_status=ASSIGNED&bug_status=REOPENED&bug_status=NEEDINFO&component=DRM%2FIntel&f0=OP&f1=OP&f2=short_desc&f3=keywords&f4=CP&f5=CP&j1=OR&known_name=i915%20regressions&list_id=600614&o2=anywordssubstr&o3=anywordss
> On Apr 24, 2017, at 10:57 AM, Ville Syrjälä
> wrote:
>
>> On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
>> Cannonlake has same color setup as Geminilake.
>> Legacy color load luts doesn't work anymore on Cannonlake+.
>
> Not sure what that means. The legacy 8bpc LUT i no lon
On Mon, Apr 24, 2017 at 10:56:40PM +0200, Rafael J. Wysocki wrote:
> On Monday, April 24, 2017 10:42:42 PM Lukas Wunner wrote:
> > On Mon, Apr 24, 2017 at 10:02:30PM +0200, Lukas Wunner wrote:
> > > On Mon, Apr 24, 2017 at 05:27:42PM +0300, Imre Deak wrote:
> > > > Some drivers - like i915 - may no
75 matches
Mail list logo
