On Mon, Apr 24, 2017 at 12:17:48AM -0700, Lionel Landwerlin wrote:
> +static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv)
> +{
> + struct i915_gem_context *ctx;
> + int ret;
> +
> + ret = i915_mutex_lock_interruptible(&dev_priv->drm);
> + if (ret)
> + return ret;
Missed a switch to kernel context, to ensure that the last context is
also saved to memory.
> +
> + /* The OA register config is setup through the context image. This image
> + * might be written to by the GPU on context switch (in particular on
> + * lite-restore). This means we can't safely update a context's image,
> + * if this context is scheduled/submitted to run on the GPU.
> + *
> + * We could emit the OA register config through the batch buffer but
> + * this might leave small interval of time where the OA unit is
> + * configured at an invalid sampling period.
> + *
> + * So far the best way to work around this issue seems to be draining
> + * the GPU from any submitted work.
> + */
> + ret = i915_gem_wait_for_idle(dev_priv,
> + I915_WAIT_INTERRUPTIBLE |
> + I915_WAIT_LOCKED);
> + if (ret) {
> + mutex_unlock(&dev_priv->drm.struct_mutex);
> + return ret;
> + }
> +
> + /* Since execlist submission may be happening asynchronously here then
> + * we first mark existing contexts dirty before we update the current
> + * context so if any switches happen in the middle we can expect
> + * that the act of scheduling will have itself ensured a consistent
> + * OA state update.
> + */
> + list_for_each_entry(ctx, &dev_priv->context_list, link) {
> + /* The actual update of the register state context will happen
> + * the next time this logical ring is submitted. (See
> + * i915_oa_update_reg_state() which hooks into
> + * execlists_update_context())
> + */
> + atomic_set(&ctx->engine[RCS].oa_state_dirty, 1);
Considering that everything is now available to be modified, you can
change the contexts right here and now and remove the checks from the
much more common path.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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