Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the 2 sets of registers.
v2:
[Jani] A
On Wed, May 6, 2015 at 1:10 PM, Paul Bolle wrote:
> On Tue, 2015-05-05 at 15:08 +0530, Shobhit Kumar wrote:
>> The Crystalcove PMIC controls PWM signals and this driver exports that
>> capability as a PWM chip driver. This is platform device implementtaion
>> of the drivers/mfd cell device for CRC
On Wed, May 6, 2015 at 5:44 PM, Thierry Reding wrote:
> On Tue, May 05, 2015 at 03:08:36PM +0530, Shobhit Kumar wrote:
>> The Crystalcove PMIC controls PWM signals and this driver exports that
>
> You say signal_s_ here, but you only expose a single PWM device. Does
> the PMIC really control more
On Tue, 05 May 2015, Daniel Vetter wrote:
> On Tue, May 05, 2015 at 11:45:05AM +0100, Lee Jones wrote:
> > This is not how we submit subsequent patch-sets.
>
> It is unfortunately how we handle patches on dri-devel&intel-gfx to be
> able to cope with massive mail load. If everyone who submits to
Add reference counting on a kernel module that exports dma-buf and
implements its operations. This prevents the module from being unloaded
while DMABUF file is in use.
The original patch [1] was submitted by Tomasz, but he's since shifted
jobs and a ping didn't elicit any response.
[tomasz: Ori
On Mon, May 04, 2015 at 07:48:20AM -0700, Todd Previte wrote:
> Updates the EDID compliance test function to perform the analyze and react to
> the EDID data read as a result of a hot plug event. The results of this
> analysis are handed off to userspace so that the userspace app can set the
> disp
On Thu, 07 May 2015, Vandana Kannan wrote:
> Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
> registers for BXT.
> BXT does not have PP_DIV register. Making changes to handle this.
> Second set of PPS registers have been defined but will be used when VBT
> provides a se
On Tue, Apr 21, 2015 at 05:12:53PM +0300, Ander Conselvan de Oliveira wrote:
> From: Maarten Lankhorst
Generally a bit too terse commmit message. E.g. here a short summary of
our irc discussion about why it should be ok to remove this feature is
definitely needed. I added that.
But I prefer more
Hi Dave,
drm-intel-next-2015-04-23:
- dither support for ns2501 dvo (Thomas Richter)
- some polish for the gtt code and fixes to finally enable the cmd parser on hsw
- first pile of bxt stage 1 enabling (too many different people to list ...)
- more psr fixes from Rodrigo
- skl rotation support fr
On Thu, May 07, 2015 at 01:00:52PM +0530, Sumit Semwal wrote:
> Add reference counting on a kernel module that exports dma-buf and
> implements its operations. This prevents the module from being unloaded
> while DMABUF file is in use.
>
> The original patch [1] was submitted by Tomasz, but he's s
On Tue, Apr 21, 2015 at 05:21:22PM +0200, Maarten Lankhorst wrote:
> Op 21-04-15 om 16:12 schreef Ander Conselvan de Oliveira:
> > Hi,
> >
> > This patch series changes the legacy modeset path to be a lot more
> > atomic like. Among other things, it
> >
> > - unifies the flip-only and the modeset
On Thu, 07 May 2015, Sonika Jindal wrote:
> The sink rate read from supported link rate table is in KHz as per spec
> while in drm, the saved clock is in deca-KHz. So divide the link rate by
> 10 before storing.
Please refer to the commit which broke things. git blame is your
friend. We need the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6325
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 07, 2015 at 11:10:30AM +0300, Jani Nikula wrote:
> On Thu, 07 May 2015, Sonika Jindal wrote:
> > The sink rate read from supported link rate table is in KHz as per spec
> > while in drm, the saved clock is in deca-KHz. So divide the link rate by
> > 10 before storing.
>
> Please refer
On Thu, May 07, 2015 at 09:52:08AM +0530, Sonika Jindal wrote:
> Renaming gen9_rates to skl_rates because other platforms may have different
> supported rates.
>
> Signed-off-by: Sonika Jindal
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 10 +-
> 1 file chang
The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.
Reading of rates was added by:
commit fc0f8e25318f ("drm/i915/skl: Read sink supported rates from edp
panel")
Cc: Ville Syrjälä
Sign
On Thu, May 07, 2015 at 09:52:09AM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> Signed-off-by: Sonika Jindal
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 44
On 05/06/2015 07:17 PM, Konduru, Chandra wrote:
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Wednesday, May 06, 2015 2:29 AM
To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko; Wood, Thomas
Subject: Re: [PATCH i-g-t 4/4] kms
On Thu, 07 May 2015, Sonika Jindal wrote:
> The sink rate read from supported link rate table is in KHz as per spec
> while in drm, the saved clock is in deca-KHz. So divide the link rate by
> 10 before storing.
>
> Reading of rates was added by:
> commit fc0f8e25318f ("drm/i915/skl: Read sink sup
On 5/7/2015 2:11 PM, Ville Syrjälä wrote:
On Thu, May 07, 2015 at 09:52:09AM +0530, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
Signed-off-by: Sonika Jindal
---
drive
On 05/06/2015 09:47 PM, Konduru, Chandra wrote:
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Tuesday, May 05, 2015 2:53 AM
To: Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko; Konduru, Chandra; Wood, Thomas
Subject: [PATCH v2 i-g-t 1/4] igt_km
On 05/06/2015 09:56 PM, Konduru, Chandra wrote:
@@ -1765,14 +1765,6 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
igt_fb *fb)
plane->fb = fb;
/* hack to keep tests working that don't call igt_plane_set_size() */
if (fb) {
- plane->crtc_w = fb->width;
-
On Thu, 23 Apr 2015, Chris Wilson wrote:
> [cc'ing the authors]
This has been posted earlier [1] and it has review to be addressed [2].
BR,
Jani.
[1] http://mid.gmane.org/1428790644-6812-1-git-send-email-ism...@iodev.co.uk
[2] http://mid.gmane.org/1428928418.2654.8.ca...@gmail.com
>
> On Sat
On Thu, May 07, 2015 at 08:52:54AM +0200, Daniel Vetter wrote:
> On Wed, May 06, 2015 at 03:51:52PM +0530, ankitprasad.r.sha...@intel.com
> wrote:
> > From: Ankitprasad Sharma
> >
> > This patch adds the testcases for verifying the new extended
> > gem_create ioctl. By means of this extended ioc
On 05/06/2015 08:02 PM, Konduru, Chandra wrote:
diff --git a/lib/igt_kms.c b/lib/igt_kms.c index b5ba273..0665d70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1765,9 +1765,7 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
igt_fb *fb)
plane->fb = fb;
/* hack to keep te
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6326
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>
> VCO calculated based on the formula:
> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz
On Wed, May 06, 2015 at 05:18:01PM +0200, Daniel Vetter wrote:
> This was accidentally lost in
>
> commit 75d04a3773ecee617847de963ae4195d6aa74c28
> Author: Mika Kuoppala
> Date: Tue Apr 28 17:56:17 2015 +0300
>
> drm/i915/gtt: Allocate va range only if vma is not bound
>
> While at it im
On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
> On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
> > [ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
> > (null)
> > [ 1572.421010] IP: []
> > ftrace_raw_event_i915_context+0x5d/0x70 [i9
Since the introduction of BIOS fb preservation, circa 3.17, we began
encountering a failure during boot when trying to use force-detect
before GEM was initialised. That bug is from
commit 7fad798e16fecddd41c6a91728a09f0b9507e40c
Author: Daniel Vetter
Date: Wed Jul 4 17:51:47 2012 +0200
drm
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6328
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 7 May 2015 at 13:40, Greg KH wrote:
> On Thu, May 07, 2015 at 01:00:52PM +0530, Sumit Semwal wrote:
>> Add reference counting on a kernel module that exports dma-buf and
>> implements its operations. This prevents the module from being unloaded
>> while DMABUF file is in use.
>>
>> The original
Reading a single value from the object, the locking only provides futile
protection against userspace races. The locking is useless so remove it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6329
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 05/06/2015 04:56 AM, Daniel Vetter wrote:
> On Tue, May 05, 2015 at 11:57:42AM -0400, Peter Hurley wrote:
>> On 05/05/2015 11:42 AM, Daniel Vetter wrote:
>>> On Tue, May 05, 2015 at 10:36:24AM -0400, Peter Hurley wrote:
On 05/04/2015 12:52 AM, Mario Kleiner wrote:
> On 04/16/2015 03:03
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6330
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, 07 May 2015, Chris Wilson wrote:
> Since the introduction of BIOS fb preservation, circa 3.17, we began
> encountering a failure during boot when trying to use force-detect
> before GEM was initialised. That bug is from
>
> commit 7fad798e16fecddd41c6a91728a09f0b9507e40c
> Author: Daniel V
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VBT contains the backlight modulation frequency
Make it available outside of intel_dp.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 34 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 34 inse
Found this while cleaning up some old branches I have in my repo...
I'm posting this more as archival for posterity than as a serious
attempt to get this merged. There was a bunch of archeology involved in
figuring out the Hz to PWM modulation frequency conversion, so someone
might find that usefu
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
> Making lane stagger calculation common for HDMI and DP
>
> Signed-off-by: Vandana Kannan
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gp
On Thu, May 07, 2015 at 10:12:08AM +0100, Chris Wilson wrote:
> On Thu, May 07, 2015 at 08:52:54AM +0200, Daniel Vetter wrote:
> > On Wed, May 06, 2015 at 03:51:52PM +0530, ankitprasad.r.sha...@intel.com
> > wrote:
> > > From: Ankitprasad Sharma
> > >
> > > This patch adds the testcases for veri
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 49e4610..cdbdf49 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3f1a784..ac1ad44 100644
--- a/drivers/gpu/drm/i915/intel_ringbuff
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cdbdf49..3f1a784 100644
--- a/drivers/gpu/drm/i915/intel_ringbu
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7ef9a29..49e4610 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
The following patch series either enables a workaround for Broxton, marks
it as applicable to Broxton, or moves it in to the SoC specific initialisation.
v2: Split out the changes as one patch per workaround (Requested by Imre)
Removed unused additional register.
Cleaned up whitespace. (Im
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e5c9f9a..001343f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dec0e74..cf36c6b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 076d3e5..dec0e74 100644
--- a/drivers/gpu/drm
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ac1ad44..076d3e5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuff
On Thu, May 07, 2015 at 11:35:40AM +0300, Ville Syrjälä wrote:
> On Thu, May 07, 2015 at 09:52:08AM +0530, Sonika Jindal wrote:
> > Renaming gen9_rates to skl_rates because other platforms may have different
> > supported rates.
> >
> > Signed-off-by: Sonika Jindal
>
> Reviewed-by: Ville Syrjälä
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cf36c6b..e5c9f9a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
On Thu, May 07, 2015 at 12:14:55PM +0100, Chris Wilson wrote:
> Reading a single value from the object, the locking only provides futile
> protection against userspace races. The locking is useless so remove it.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem.c | 17 ---
On Thu, May 07, 2015 at 03:22:41PM +0200, Daniel Vetter wrote:
> On Thu, May 07, 2015 at 12:14:55PM +0100, Chris Wilson wrote:
> > Reading a single value from the object, the locking only provides futile
> > protection against userspace races. The locking is useless so remove it.
> >
> > Signed-of
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6331
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote:
> On Thu, 23 Apr 2015, Chris Wilson wrote:
> > [cc'ing the authors]
>
> This has been posted earlier [1] and it has review to be addressed [2].
>
> BR,
> Jani.
I agree with Ander's response in [2]...we can't call
intel_update_watermar
Am 2015-05-04 um 13:24 schrieb Jani Nikula:
> On Mon, 04 May 2015, Martin Kepplinger wrote:
>> So. -rc1 broke suspending by closing my laptop lid and it's not fixed in
>> -rc2. It works exactly *one* first time and every subsequent lid-closing
>> is ignored.
>>
>> Biscted and tested first bad comm
Inluding extended didl and cpdl fields
Present since opregion version 3.0.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/inte
Adding support for did2, or the extended support display devices ID
list, increases the total to 15.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_o
Conform to same style as the rest of the driver.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index d05a504fd176..
Make it easier to handle the extended didl. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 50 +++
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/d
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 71e87abdcae7..c4756a2d77bb 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/dr
On Thu, 07 May 2015, Matt Roper wrote:
> On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote:
>> On Thu, 23 Apr 2015, Chris Wilson wrote:
>> > [cc'ing the authors]
>>
>> This has been posted earlier [1] and it has review to be addressed [2].
>>
>> BR,
>> Jani.
>
> I agree with Ander's r
Chris Wilson writes:
> Reading a single value from the object, the locking only provides futile
> protection against userspace races. The locking is useless so remove it.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem.c | 17 -
On Thu, 07 May 2015, Martin Kepplinger wrote:
> Am 2015-05-04 um 13:24 schrieb Jani Nikula:
>> On Mon, 04 May 2015, Martin Kepplinger wrote:
>>> So. -rc1 broke suspending by closing my laptop lid and it's not fixed in
>>> -rc2. It works exactly *one* first time and every subsequent lid-closing
>>
Improve readability. No functional changes.
Signed-off-by: Jani Nikula
---
Cleaning up old branches... :)
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 52
1 file changed, 17 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/
The PERF_PMU_CAP_IS_DEVICE flag provides pmu drivers a way to declare
that they only monitor device specific metrics and since they don't
monitor any cpu metrics then perf should bypass any cpu centric security
checks, as well as disallow cpu centric attributes.
Signed-off-by: Robert Bragg
---
i
This exports enough api to allow drivers to output their own
PERF_RECORD_DEVICE events.
Signed-off-by: Robert Bragg
---
include/linux/perf_event.h | 7 +++
kernel/events/core.c| 2 ++
kernel/events/internal.h| 9 -
kernel/events/ring_buffer.c | 3 +++
4 files changed, 12
Gen graphics hardware can be set up to periodically write snapshots of
performance counters into a circular buffer and this patch exposes that
capability to userspace via the perf interface.
To start with this only enables the A (aggregating) counters with the
simplest configuration requirements.
This adds two driver specific PERF_RECORD_DEVICE event types for
reporting OA buffer overrun and report lost status bits to userspace.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_oa_perf.c | 53 -
include/uapi/drm/i915_drm.h | 27
This enables access to some additional counters beyond the aggregating A
counters, adding a '3D' metric set configuration useful while profiling
3D rendering workloads.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_oa_perf.c | 124
To support pmu drivers in loadable modules, such as the i915 driver
Signed-off-by: Robert Bragg
---
kernel/events/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 2fabc06..38c240c 100644
--- a/kernel/events/core.c
+++ b/kernel/events/co
We are still investigating the detailed requirements here, but there are
some constraints we need to apply on unit level clock gating for
reliable metrics (in particular for a reliable sampling period).
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_oa_perf.c | 70
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h| 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a
Consistent with the kernel.perf_event_paranoid sysctl option that can
allow non-root users to access system wide cpu metrics, this can
optionally allow non-root users to access system wide OA counter metrics
from Gen graphics hardware.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_dr
This is an updated series adding support for an "i915_oa" perf PMU for
configuring the Intel Gen graphics Observability unit (Haswell only to
start with) and forwarding periodic counter reports as perf samples.
Compared to the series I sent out last year:
The driver is now hooked into context swi
To allow for more extensible, device specific, perf record types this
adds a generic PERF_RECORD_DEVICE type that can be used by device
drivers. Driver developers can then document some driver-specific header
to further detail such a record's type.
Signed-off-by: Robert Bragg
---
include/uapi/li
To allow for pmus that may have internal buffering (e.g. the hardware
itself writes out data to its own circular buffer which is only
periodically forwarded to userspace via perf) this ioctl enables
userspace to explicitly ensure it has received all samples before a
point in time.
Signed-off-by: R
On Thu, May 07, 2015 at 04:41:48PM +0300, Jani Nikula wrote:
> On Thu, 07 May 2015, Matt Roper wrote:
> > On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote:
> >> On Thu, 23 Apr 2015, Chris Wilson wrote:
> >> > [cc'ing the authors]
> >>
> >> This has been posted earlier [1] and it has r
On Thu, May 07, 2015 at 03:15:46PM +0100, Robert Bragg wrote:
> To allow for pmus that may have internal buffering (e.g. the hardware
> itself writes out data to its own circular buffer which is only
> periodically forwarded to userspace via perf) this ioctl enables
> userspace to explicitly ensure
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6332
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 07, 2015 at 03:15:50PM +0100, Robert Bragg wrote:
> +static int init_oa_buffer(struct perf_event *event)
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(event->pmu, typeof(*dev_priv), oa_pmu.pmu);
> + struct drm_i915_gem_object *bo;
> + int ret;
> +
On Thu, May 07, 2015 at 03:15:50PM +0100, Robert Bragg wrote:
> + /* We bypass the default perf core perf_paranoid_cpu() ||
> + * CAP_SYS_ADMIN check by using the PERF_PMU_CAP_IS_DEVICE
> + * flag and instead authenticate based on whether the current
> + * pid owns the specified
On to, 2015-05-07 at 14:15 +0100, Nick Hoath wrote:
> The following patch series either enables a workaround for Broxton, marks
> it as applicable to Broxton, or moves it in to the SoC specific
> initialisation.
>
> v2: Split out the changes as one patch per workaround (Requested by Imre)
> R
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6333
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 07, 2015 at 04:36:48PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
On 05/06/2015 07:48 AM, Patrik Jakobsson wrote:
> This patch set aims to make strace more useful when tracing i915 ioctls.
> The ioctl type is first checked for being drm and then the driver
> backing the opened device is identified by looking at sysfs. Other
> drivers than i915 can easily be added
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Wednesday, May 06, 2015 11:59 PM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Syrjala, Ville
> Subject: Re: [Intel-gfx] [PATCH 09/11] drm/i915: Up
On Thu, May 07, 2015 at 06:17:03PM +0300, Imre Deak wrote:
> On to, 2015-05-07 at 14:15 +0100, Nick Hoath wrote:
> > The following patch series either enables a workaround for Broxton, marks
> > it as applicable to Broxton, or moves it in to the SoC specific
> > initialisation.
> >
> > v2: Split
On Wed, May 06, 2015 at 02:40:48PM +0300, Joonas Lahtinen wrote:
> On ke, 2015-05-06 at 12:20 +0200, Daniel Vetter wrote:
> > On Thu, Apr 30, 2015 at 01:16:30PM +0100, Tvrtko Ursulin wrote:
> > > On 04/30/2015 12:20 PM, Joonas Lahtinen wrote:
> > > >@@ -495,7 +503,10 @@ i915_ggtt_view_equal(const s
On Wed, May 06, 2015 at 01:24:18PM +0100, Tvrtko Ursulin wrote:
>
>
> On 05/06/2015 12:35 PM, Joonas Lahtinen wrote:
> >
> >Partial view type allows manipulating parts of huge BOs through the GGTT,
> >which was not previously possible due to constraint that whole object had
> >to be mapped for an
The kernel code will follow with all the explanations, but here is the testing
code. It's quite handy to have this in userspace to be a bit more exhaustive in
the testing that what we can do in the kernel.
--
Damien
Damien Lespiau (5):
compute_wrpll: Rename ddi_compute_wrpll to hsw_compute_wrp
Signed-off-by: Damien Lespiau
---
tools/skl_compute_wrpll.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tools/skl_compute_wrpll.c b/tools/skl_compute_wrpll.c
index a3a6e58..55f2df4 100644
--- a/tools/skl_compute_wrpll.c
+++ b/tools/skl_compute_wrpll.c
@@ -431,6 +431,13 @@ skl_ddi_c
I had various problems (infinite loops, unable to compute dividers for
certain frequencies) after implementing a BSpec update. Much easier to
debug that in userspace.
Signed-off-by: Damien Lespiau
---
tools/.gitignore | 1 +
tools/Makefile.sources| 1 +
tools/skl_compute_wrpll.c
We're going to add the SKL version, time to rename the HSW/BDW one.
Signed-off-by: Damien Lespiau
---
tools/.gitignore | 2 +-
tools/Makefile.sources | 2 +-
tools/{ddi_compute_wrpll.c => hsw_compute_wrpll.c} | 0
3 files changed, 2 i
Signed-off-by: Damien Lespiau
---
tools/skl_compute_wrpll.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/tools/skl_compute_wrpll.c b/tools/skl_compute_wrpll.c
index 4f7ea9a..a3a6e58 100644
--- a/tools/skl_compute_wrpll.c
+++ b/tools/skl_compute_wrpll.c
@@ -8
We might as well verify that we have a semblance of all being in order
by making sure the DCO frequency is within the expected bounds.
Signed-off-by: Damien Lespiau
---
tools/skl_compute_wrpll.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/tools
On 05/07/2015 01:56 PM, Peter Hurley wrote:
On 05/06/2015 04:56 AM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 11:57:42AM -0400, Peter Hurley wrote:
On 05/05/2015 11:42 AM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 10:36:24AM -0400, Peter Hurley wrote:
On 05/04/2015 12:52 AM, Mario Klein
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