On 7/3/2025 12:54 AM, Ville Syrjälä wrote:
On Wed, Jul 02, 2025 at 09:42:04AM +, Borah, Chaitanya Kumar wrote:
-Original Message-
From: Jani Nikula
Sent: Wednesday, July 2, 2025 2:01 PM
To: Borah, Chaitanya Kumar ; intel-
x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.o
On 7/2/2025 7:42 PM, Jani Nikula wrote:
On Wed, 02 Jul 2025, Gustavo Sousa wrote:
Quoting Ankit Nautiyal (2025-07-02 05:46:18-03:00)
Introduce a generic helper to check display workarounds using an enum.
Convert Wa_16023588340 to use the new interface, simplifying WA checks
and making futur
On 7/2/2025 6:41 PM, Gustavo Sousa wrote:
Quoting Ankit Nautiyal (2025-07-02 05:46:19-03:00)
As per Wa_16025573575 for PTL, set the GPIO masks bit before starting
bit-bashing and maintain value through the bit-bashing sequence.
After bit-bashing sequence is done, clear the GPIO masks bits.
v2
Hi Dave & Sima,
Here's drm-intel-fixes towards 6.16-rc5.
Fix for mei interrupt handling on RT builds, two NULL deref fixes
and one memory leak fix.
Regards, Joonas
***
drm-intel-fixes-2025-07-03:
- Make mei interrupt top half irq disabled to fix RT builds
- Fix timeline left held on VMA alloc
== Series Details ==
Series: drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
URL : https://patchwork.freedesktop.org/series/151097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16791 -> Patchwork_151097v1
Su
== Series Details ==
Series: series starting with [1/4] iopoll: Generalize read_poll_timeout() into
poll_timeout_us()
URL : https://patchwork.freedesktop.org/series/151094/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16790 -> Patchwork_151094v1
=
On Wed, 2025-07-02 at 11:14 +0300, Jani Nikula wrote:
> On Wed, 02 Jul 2025, "Almahallawy, Khaled"
> wrote:
> > On Tue, 2025-07-01 at 21:50 +, Cavitt, Jonathan wrote:
> > > -Original Message-
> > > From: Intel-gfx On
> > > Behalf
> > > Of Khaled Almahallawy
> > > Sent: Tuesday, July 1
Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
4.2.2.1 test states [1]:
"Fail1: Source DUT failed to read the DPCD Receiver Capability field
(DPCD:0h:Fh) through AUX_CH before link training."
4.2.2.2 test stat
From: Ville Syrjälä
Make sure poll_timeout_us() works by using it in i915
instead of the custom __wait_for().
Remaining difference between two:
| poll_timeout_us() | __wait_for()
---
backoff| fixed interval| exponential
u
From: Ville Syrjälä
Currently poll_timeout_us() evaluates 'op' and 'cond' twice
within the loop, once at the start, and a second time after
the timeout check. While it's probably not a big deal to do
it twice almost back to back, it does make the macro a bit messy.
Simplify the implementation to
From: Ville Syrjälä
While read_poll_timeout() & co. were originally introduced just
for simple I/O usage scenarios they have since been generalized to
be useful in more cases.
However the interface is very cumbersome to use in the general case.
Attempt to make it more flexible by combining the '
From: Ville Syrjälä
Currently poll_timeout_us() evaluates 'cond' twice at the end
of the success case. This not desirable in case 'cond' itself
is expensive.
Avoid the double evaluation by tracking the return value in
a variable. Need to use a triple undescore '___ret' name to
avoid a conflict w
On Thu, Jul 03, 2025 at 12:29:37AM +0300, Ville Syrjälä wrote:
> On Wed, Jul 02, 2025 at 03:25:21PM -0500, Lucas De Marchi wrote:
> > On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
> > >On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
> > >> Introduce a generic helper
On Wed, Jul 02, 2025 at 03:25:21PM -0500, Lucas De Marchi wrote:
> On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
> >On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
> >> Introduce a generic helper to check display workarounds using an enum.
> >>
> >> Convert Wa_16023
On Mon, Jun 30, 2025 at 04:41:08PM +0200, Jocelyn Falempe wrote:
There is an unneeded blank line in the documentation of the function
ttm_bo_kmap_try_from_panic().
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202506290453.netxab7s-...@intel.com/
Fixes: 718370ff2
On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
Introduce a generic helper to check display workarounds using an enum.
Convert Wa_16023588340 to use the new interface, simplifying WA checks
and making future addition
在 2025/6/27 23:45, Matthew Wilcox 写道:
On Fri, Jun 27, 2025 at 11:03:11AM +, 陈涛涛 Taotao Chen wrote:
diff --git a/fs/exfat/file.c b/fs/exfat/file.c
index 841a5b18e3df..fdc2fa1e5c41 100644
--- a/fs/exfat/file.c
+++ b/fs/exfat/file.c
@@ -532,10 +532,12 @@ int exfat_file_fsync(struct file *filp
On Tue, Jul 01, 2025 at 05:38:21PM +, Almahallawy, Khaled wrote:
> Thank you for your patch. This fix enables us to pass the DP1.4 Link
> Layer Test "4.2.2.8 EDID Read on IRQ HPD Event after Branch Device
> Detection," which was failing due to the following error:
>
> "0003.610.625: Main Strea
On Wed, Jul 02, 2025 at 09:42:04AM +, Borah, Chaitanya Kumar wrote:
>
>
> > -Original Message-
> > From: Jani Nikula
> > Sent: Wednesday, July 2, 2025 2:01 PM
> > To: Borah, Chaitanya Kumar ; intel-
> > x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre ;
On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
> Introduce a generic helper to check display workarounds using an enum.
>
> Convert Wa_16023588340 to use the new interface, simplifying WA checks
> and making future additions easier.
>
> v2: Use drm_WARN instead of MISSING_CASE an
== Series Details ==
Series: drm/i915: replace DRM_DEBUG_SELFTEST with DRM_KUNIT_TEST (rev2)
URL : https://patchwork.freedesktop.org/series/151085/
State : failure
== Summary ==
Address 'rubenr...@aol.com' is not on the allowlist, which prevents CI from
being triggered for this patch.
If you
On Tue, 2025-07-01 at 09:28 +0300, Jani Nikula wrote:
> On Tue, 01 Jul 2025, Ruben Wauters wrote:
> > DRM_DEBUG_SELFTEST was replaced with DRM_KUNIT_TEST.
> >
> > This patch replaces the select in Kconfig.debug to use the
> > replacement.
>
> Why? That's the most important questions the commit m
DRM_DEBUG_SELFTEST was removed in commit fc8d29e298cf (drm: selftest:
convert drm_mm selftest to KUnit) and all functions under it were
converted to KUnit, under the DRM_KUNIT_TEST option
This conversion however did not occur in the Kconfig.debug file in the
i915 directory.
This patch replaces th
在 2025/6/27 23:52, Matthew Wilcox 写道:
On Fri, Jun 27, 2025 at 11:03:11AM +, 陈涛涛 Taotao Chen wrote:
@@ -1399,13 +1400,10 @@ static int write_end_fn(handle_t *handle, struct inode
*inode,
}
/*
- * We need to pick up the new inode size which generic_commit_write gave us
- * `file' c
On Tue, 2025-07-01 at 03:50 +0100, Ruben Wauters wrote:
> DRM_DEBUG_SELFTEST was replaced with DRM_KUNIT_TEST.
>
> This patch replaces the select in Kconfig.debug to use the
> replacement.
>
> Signed-off-by: Ruben Wauters
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 2 +-
> 1 file changed, 1 in
DRM_DEBUG_SELFTEST was replaced with DRM_KUNIT_TEST.
This patch replaces the select in Kconfig.debug to use the replacement.
Signed-off-by: Ruben Wauters
---
drivers/gpu/drm/i915/Kconfig.debug | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
Hi Jani,
On Thu, Jun 26, 2025 at 05:51:19PM +0300, Jani Nikula wrote:
> Sometimes it's necessary to poll with long sleeps, and the accuracy of
> usleep_range() is overkill. Use the flexible sleep helper fsleep() for
> sleeping in the read_poll_timeout() family of macros to automatically
> choose t
On Wed, 02 Jul 2025, Gustavo Sousa wrote:
> Quoting Ankit Nautiyal (2025-07-02 05:46:18-03:00)
>>Introduce a generic helper to check display workarounds using an enum.
>>
>>Convert Wa_16023588340 to use the new interface, simplifying WA checks
>>and making future additions easier.
>>
>>v2: Use drm
Quoting Ankit Nautiyal (2025-07-02 05:46:18-03:00)
>Introduce a generic helper to check display workarounds using an enum.
>
>Convert Wa_16023588340 to use the new interface, simplifying WA checks
>and making future additions easier.
>
>v2: Use drm_WARN instead of MISSING_CASE and simplify intel_di
Quoting Ankit Nautiyal (2025-07-02 05:46:19-03:00)
>As per Wa_16025573575 for PTL, set the GPIO masks bit before starting
>bit-bashing and maintain value through the bit-bashing sequence.
>After bit-bashing sequence is done, clear the GPIO masks bits.
>
>v2:
>-Use new helper for display workarounds
Hi,
https://patchwork.freedesktop.org/series/150813/ - Re-reported.
i915.CI.BAT - Re-reported.
Thanks,
Ravali.
-Original Message-
From: I915-ci-infra On Behalf Of
Jani Nikula
Sent: 26 June 2025 20:55
To: i915-ci-in...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: R
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev5)
URL : https://patchwork.freedesktop.org/series/129811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16786 -> Patchwork_129811v5
Summary
-
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, July 2, 2025 2:13 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> intel...@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ;
> ville.syrj...@linux.intel.com; Almahallawy, Khaled
> ; Shankar, Uma
> Subject: Re: [P
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Tuesday, July 1, 2025 2:21 PM
> To: dri-de...@lists.freedesktop.org; intel...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ;
> linux-n...@vger.kernel.org;
> s...@canb.auug.org
== Series Details ==
Series: Introduce helper for display workarounds and add Wa_16025573575 (rev2)
URL : https://patchwork.freedesktop.org/series/150936/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16786 -> Patchwork_150936v2
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, July 2, 2025 2:01 PM
> To: Borah, Chaitanya Kumar ; intel-
> x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre ; ville.syrj...@linux.intel.com; Shankar,
> Uma ; Borah, Chaitanya Kumar
>
> Subject: Re
On Wed, 02 Jul 2025, Ankit Nautiyal wrote:
> Introduce a generic helper to check display workarounds using an enum.
>
> Convert Wa_16023588340 to use the new interface, simplifying WA checks
> and making future additions easier.
>
> v2: Use drm_WARN instead of MISSING_CASE and simplify intel_displ
== Series Details ==
Series: drm/i915/display: Add upper limit check for pixel clock
URL : https://patchwork.freedesktop.org/series/151048/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16785 -> Patchwork_151048v1
Summary
-
== Series Details ==
Series: drm/i915/display: drop a number of dependencies on i915_drv.h
URL : https://patchwork.freedesktop.org/series/150813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16760 -> Patchwork_150813v1
Sum
Add documentation to explain properties of the exposed hardware
1D LUT blocks, its identification and computation of the LUT samples
based on the number of samples, their distribution and precison.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
Documentation/gpu/rfc/color_p
From: Chaitanya Kumar Borah
Add a color pipeline with three colorops in the sequence
1D LUT MULTSEG - CTM - 1D LUT MULTSEG
This pipeline can be used to do any color space conversion or HDR
tone mapping
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/d
From: Chaitanya Kumar Borah
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/drm/i915/display/skl_universal_plane.c | 17 +
1 file changed, 17 insertions(
From: Chaitanya Kumar Borah
Extract the LUT and program plane post csc registers.
v2: Add DSB support
v3: Add support for single segment 1D LUT
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 123 +
1 file c
From: Chaitanya Kumar Borah
Add callback for programming Pre-CSC LUT for TGL and beyond
v2: Add DSB support
v3: Add support for single segment 1D LUT color op
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 104
Add macros to define Plane Post CSC registers
v2: Add Plane Post CSC Gamma Multi Segment Enable bit
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 74 +++
1 file changed, 74 insertions(+)
diff --git a/drivers
From: Chaitanya Kumar Borah
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
v2: Add dsb support
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 16
.../gpu/drm/i915/display/intel_display_types.h | 2 +-
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/driv
Add callback for setting CTM block in platforms D13 and beyond
v2:
- Add dsb support
- Pass plane_state as we are now doing a uapi to hw state copy
- Add support for 3x4 matrix
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 96 +
From: Chaitanya Kumar Borah
When int_bits == 0, we lose the sign bit when we do the range check
and apply the mask.
Fix this by ensuring a minimum of one integer bit, which guarantees space
for the sign bit in fully fractional representations (e.g. S0.12)
Signed-off-by: Chaitanya Kumar Borah
S
From: Chaitanya Kumar Borah
Since we intend to add plane color callbacks from Xelpd(D13 and beyond),
create a different structure for it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++-
1 file changed, 14 ins
From: Chaitanya Kumar Borah
Add callback to intel color functions for setting plane CTM.
v2: adapt to struct intel_display
v3: add dsb support
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 10 +-
1 file changed, 9 ins
From: Chaitanya Kumar Borah
Add supported color pipelines and attach it to plane.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 42 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 45
From: Chaitanya Kumar Borah
Add framework to program CSC. It enables copying of matrix from uapi
to intel plane state. Also adding helper functions which will eventually
program values to hardware.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/displa
From: Chaitanya Kumar Borah
Add a color pipeline with three colorops in the sequence
1D LUT - 3x4 CTM - 1D LUT
This pipeline can be used to do any color space conversion or HDR
tone mapping
v2: Change namespace to drm_plane_colorop*
v3: Use simpler/pre-existing colorops for first itera
From: Chaitanya Kumar Borah
Add intel colorop create helper
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 39 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 42 insertions(+)
diff -
From: Chaitanya Kumar Borah
Add data structure to store intel specific details of colorop
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/
From: Chaitanya Kumar Borah
Add macros to identify intel color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 13 +
1 file changed, 13
From: Chaitanya Kumar Borah
Add helper to extract lut values in the precision needed by
hardware.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
include/drm/drm_color_mgmt.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/drm/drm_color_mgmt.h
This adds helper functions to create 1D multi-segmented Lut
color block capabilities. It exposes the hardware block as segments
which are converted to blob and passed in the property.
This also adds helper to initialize 1D segmented LUT.
v2: Squashed the 1d lut helpers (Dmitry)
v3: Change name spa
From: Chaitanya Kumar Borah
Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.
v2: Fixed the documentation for Multi segmented lut (Dmitry)
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c |
Add capability property which a colorop can expose it's
hardware's abilities. It's a blob property that can be
filled with respective data structures depending on the
colorop. The user space is expected to read this property
and program the colorop accordingly.
v2: Added documentation for hw_caps
This defines a new structure to define color lut ranges,
along with related macro definitions and enums. This will help
describe segmented lut ranges/PWL LUTs in the hardware.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
include/uapi/drm/drm_mode.h | 64 ++
This series intends to add support for Plane Color Management for
Intel platforms. This is based on the design which has been agreed
upon by the community. Series implementing the design for generic
DRM core has been sent out by Alex Hung and Harry Wentland and is under
review below:
https://patchw
On Tue, 01 Jul 2025, Lucas De Marchi wrote:
> On Tue, Jul 01, 2025 at 12:28:41PM +0300, Jani Nikula wrote:
>>On Mon, 30 Jun 2025, Dibin Moolakadan Subrahmanian
>> wrote:
>>> The current wait_panel_on() uses intel_de_wait() with a long timeout
>>> (5000ms), which is suboptimal on Xe platforms wh
As per Wa_16025573575 for PTL, set the GPIO masks bit before starting
bit-bashing and maintain value through the bit-bashing sequence.
After bit-bashing sequence is done, clear the GPIO masks bits.
v2:
-Use new helper for display workarounds. (Jani)
-Use a separate if-block for the workaround. (Gu
Introduce a generic helper to check display workarounds using an enum.
Convert Wa_16023588340 to use the new interface, simplifying WA checks
and making future additions easier.
v2: Use drm_WARN instead of MISSING_CASE and simplify intel_display_wa
macro. (Jani)
Suggested-by: Jani Nikula
Signed
This series introduces a generic infrastructure for querying display
workarounds. The goal is to simplify WA checks, avoid open-coded conditions,
and make it easier to extend support for future workarounds.
Patch 1 introduces the base infrastructure using an enum and a central
helper function. It
On Wed, 02 Jul 2025, Chaitanya Kumar Borah
wrote:
> Add upper limit check for pixel clock by platform. Limits don't apply
> when DSC is enabled.
>
> For the currently supported versions of HDMI, pixel clock is already
> limited to 600Mhz so nothing needs to be done there as of now.
>
> BSpec: 491
On Tue, 01 Jul 2025, Uma Shankar wrote:
> RGB limited range should be selected only if explicitly asked by
> userspace by the broadcast RGB property with LIMITED_RANGE. This
> is mostly enabled in case of CEA modes.
>
> Display port by default uses Full Range, fixed the same. This will help
> set
On Wed, 02 Jul 2025, "Almahallawy, Khaled" wrote:
> On Tue, 2025-07-01 at 21:50 +, Cavitt, Jonathan wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf
>> Of Khaled Almahallawy
>> Sent: Tuesday, July 1, 2025 12:27 PM
>> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedes
Hi Dave, Sima,
Here comes the first pull request for 6.17.
Headline feature is that Ville was able to move DG1 out of force probe.
Other than that mostly fixes in the GuC backend.
One cross-merge to fix the build.
Regards,
Tvrtko
drm-intel-gt-next-2025-07-02:
Driver Changes:
Fixes/improvemen
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