Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
4.2.2.1 test states [1]:
"Fail1: Source DUT failed to read the DPCD Receiver Capability field
(DPCD:00000h:0000Fh) through AUX_CH before link training."
4.2.2.2 test states [1]:
"Fail2: Source DUT failed to read the DPCD Extended Receiver Capability
field (DPCD:02200h:0220Fh) through AUX_CH before link training."
Additionally, the spec [2] states:
"The Source device shall respond to Hot Plug event/Hot Re-plug event by
first reading DPCD Link/Sink Device Status registers at DPCD 00200h
through 00205h βorβ DPCD 02002h through 0200Fh. If the link is unstable
or lost, the Source device then reads the DPCD Receiver Capabilities
registers at DPCD 00000h through 0000Fh to determine the appropriate
information needed to train the link. The Source device shall then
initiate link training."
Increasing DP_RECEIVER_CAP_SIZE by 1 byte ensures passing the test
conditions for these link layer tests.
[1]: DisplayPort v2.1 Link Layer Compliance Test Specification
sections 4.2.2.1 & 4.2.2.2
[2]: DisplayPort Standard v2.1 - Sec 5.1.4 Source Device Behavior
upon HPD Pulse Detection
Cc: Uma Shankar <uma.shan...@intel.com>
Cc: Sean Paul <seanp...@chromium.org>
Cc: Jonathan Cavitt <jonathan.cav...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahall...@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 811e9238a77c..960c9757ba76 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1681,7 +1681,7 @@ enum drm_dp_phy {
#define DP_LINK_STATUS_SIZE 6
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
-#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_RECEIVER_CAP_SIZE 0x10
#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through
0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 5
--
2.43.0
