On 7/3/2025 12:54 AM, Ville Syrjälä wrote:
On Wed, Jul 02, 2025 at 09:42:04AM +0000, Borah, Chaitanya Kumar wrote:
-----Original Message-----
From: Jani Nikula <jani.nik...@linux.intel.com>
Sent: Wednesday, July 2, 2025 2:01 PM
To: Borah, Chaitanya Kumar <chaitanya.kumar.bo...@intel.com>; intel-
x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Deak, Imre <imre.d...@intel.com>; ville.syrj...@linux.intel.com; Shankar,
Uma <uma.shan...@intel.com>; Borah, Chaitanya Kumar
<chaitanya.kumar.bo...@intel.com>
Subject: Re: [PATCH] drm/i915/display: Add upper limit check for pixel clock
On Wed, 02 Jul 2025, Chaitanya Kumar Borah
<chaitanya.kumar.bo...@intel.com> wrote:
Add upper limit check for pixel clock by platform. Limits don't apply
when DSC is enabled.
For the currently supported versions of HDMI, pixel clock is already
limited to 600Mhz so nothing needs to be done there as of now.
BSpec: 49199, 68912
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 456fc4b04cda..bf0faff50c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7902,6 +7902,18 @@ void intel_setup_outputs(struct intel_display
*display)
drm_helper_move_panel_connectors_to_head(display->drm);
}
+int intel_dotclock_limit(struct intel_display *display) {
+ if (DISPLAY_VERx100(display) == 3002)
+ return 937500;
+ else if (DISPLAY_VER(display) >= 30)
+ return 1350000;
+ else if (DISPLAY_VER(display) >= 13)
+ return 1200000;
+ else
+ return 1100000;
+}
How does this relate to display->cdclk.max_dotclk_freq that's computed in
intel_compute_max_dotclk(display)?
The Bspec defines this limit as "maximum validated frequency" and asks to limit
the pixel clock accordingly when DSC is not enabled.
At least for PTL it is 97.65 % of the mathematically calculated maximum pixel
clock (pixel per clock * max cdclk).
I am not sure if intel_cdclk_guardband() used in intel_compute_max_dotclk() was
intended for something similar. However, since the limit only applies
when dsc is not enabled it made sense to me that we apply this limit during
intel_dp_mode_valid () instead of doing it in intel_compute_max_dotclk().
I think what we need is something like:
- implement the DSC bubble stuff and account for it in both
cdclk calculations and mode validation
I have some patch for accounting the DSC bubble stuff for cdclk
calculations, but not for mode validation though.
https://patchwork.freedesktop.org/series/150083/
Still need to test properly.
Regards,
Ankit
- implement this non-dsc cdclk limit checks also in a way that
covers both (also needs to cover all output types, not just DP).
I suspect the DSC bubble stuff might always end up more restrictive
than this, so perhaps this could just be covered by adjusting the
cdclk guardband
