On Mon, 24 Feb 2025, Andi Shyti wrote:
> Hi Ville,
>
> On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
>> style.
>
> using REG_BIT() and co. doesn't alway make it more readable. In
> some
Hook up the newly added plane function pointer
format_mod_supported_async to populate the modifiers/formats supported
by asynchronous flips.
v5: Correct the if condition for modifier support check (Chaitanya)
v6: Replace uint32_t/uint64_t with u32/u64 (Jani)
v7: Move plannar check from intel_async
create_in_formats creates the list of supported format/modifiers for
synchronous flips, modify the same function so as to take the
format_mod_supported as argument and create list of format/modifier for
async as well.
v5: create_in_formats can return -ve value in failure case, correct the
if condi
There exists a property IN_FORMATS which exposes the plane supported
modifiers/formats to the user. In some platforms when asynchronous flip
are used all of modifiers/formats mentioned in IN_FORMATS are not
supported. This patch adds a new plane property IN_FORMATS_ASYNC to
expose the async flip su
Hi,
https://patchwork.freedesktop.org/series/145327/ - Re-reported.
i915.CI.BAT - Re-reported.
Thanks,
Ravali.
From: I915-ci-infra On Behalf Of
Gote, Nitin R
Sent: 25 February 2025 11:49
To: i915-ci-in...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.CI.BAT: f
== Series Details ==
Series: drm/i915/gt: Add a delay to let engine resumes correctly (rev2)
URL : https://patchwork.freedesktop.org/series/145327/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16175 -> Patchwork_145327v2
S
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, February 24, 2025 4:18 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Hogander, Jouni ; B, Jeevan
> ; Manna, Animesh
> Subject: Re: [PATCH v4 4/8] drm/i915/lobf: Update lobf i
Hi,
Changes introduced with this patch is not related to the below Possible
regression or failure.
Please update CBL filters and re-report.
Thanks,
Nitin
From: Patchwork
Sent: Monday, February 24, 2025 11:50 PM
To: Gote, Nitin R
Cc: intel-gfx@lists.freedesktop.
== Series Details ==
Series: drm/i915/gt: Add a delay to let engine resumes correctly (rev2)
URL : https://patchwork.freedesktop.org/series/145327/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16175 -> Patchwork_145327v2
S
Hi Animesh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on v6.14-rc4]
[also build test WARNING on linus/master next-20250224]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
== Series Details ==
Series: drm/dp: Fix link training interrupted by HPD pulse
URL : https://patchwork.freedesktop.org/series/145352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16175 -> Patchwork_145352v1
Summary
--
== Series Details ==
Series: drm/dp: Fix link training interrupted by HPD pulse
URL : https://patchwork.freedesktop.org/series/145352/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/144683/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16174 -> Patchwork_144683v3
Summary
== Series Details ==
Series: drm/i915: Fix pipeDMC and ATS fault handling
URL : https://patchwork.freedesktop.org/series/145349/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16174 -> Patchwork_145349v1
Summary
---
*
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/144683/
State : warning
== Summary ==
Error: dim checkpatch failed
067f8029ba78 drm/i915: Bump RING_FAULT engine ID bits
97af3013b359 drm/i915: Relocate RING_FAULT b
== Series Details ==
Series: drm/i915/dp: Implement POST_LT_ADJ_REQ
URL : https://patchwork.freedesktop.org/series/145348/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16174 -> Patchwork_145348v1
Summary
---
**SUCCE
== Series Details ==
Series: drm/i915/dp: Implement POST_LT_ADJ_REQ
URL : https://patchwork.freedesktop.org/series/145348/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dp: Implement POST_LT_ADJ_REQ
URL : https://patchwork.freedesktop.org/series/145348/
State : warning
== Summary ==
Error: dim checkpatch failed
de7e728f1294 drm/dp: Add definitions for POST_LT_ADJ training sequence
a2f2624751cc drm/dp: Add POST_LT_ADJ_REQ
== Series Details ==
Series: drm/i915: reduce display dependencies on core
URL : https://patchwork.freedesktop.org/series/145341/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16172 -> Patchwork_145341v1
Summary
---
== Series Details ==
Series: drm/i915: reduce display dependencies on core
URL : https://patchwork.freedesktop.org/series/145341/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: reduce display dependencies on core
URL : https://patchwork.freedesktop.org/series/145341/
State : warning
== Summary ==
Error: dim checkpatch failed
ffecd381b7bf drm/i915: relocate intel_plane_ggtt_offset() to
intel_atomic_plane.c
ed8ba8b5e8ef drm/i915:
During Display Port link training the handling of HPD pulses should be
prevented, as that handling can interfere with the link training:
- Accessing DPCD registers outside the range of link training registers
are not allowed by the Standard (see DP Standard v2.1, 3.5.2.16.1,
3.6.6.1). The puls
After link training - both in case of a passing and failing LT result -
a work is scheduled to check the link state. This check should take
place after the link training is completed by disabling the link
training pattern and setting intel_dp::link_trained=true. Atm, the work
is scheduled before th
After suspending and resuming the detection on connectors, HPD IRQs that
arrived while the detection was suspended, are handled by scheduling the
intel_hotplug::hotplug work for them. All HPD pins must be at this point
in either the HPD_ENABLED (set for all pins during driver loading/system
resumin
intel_hpd_disable/enable() have the same purpose as
intel_hpd_suspend/resume(), except that disable/enable will drop any HPD
IRQs which were triggered while the HPD was disabled, while
suspend/resume will handle such IRQs after the IRQ handling is resumed.
Use intel_hpd_suspend/resume() for crt as
Add support for suspending the IRQ handling on the HPD pin of a given
encoder, handling IRQs that arrived while in the suspended state after
resuming the IRQ handling. This will be used by a follow-up change,
which suspends/resumes the IRQ handling around DP link training.
This is similar to the i
This patchset fixes a problem during Display Port link training, where
the link training is interrupted by a short HPD pulse generated by the
sink. Generally the sink signals a bad link state via such short pulses,
but the sink should prevent such signaling during link training.
Some sinks do gene
== Series Details ==
Series: LOBF enablement fix (rev4)
URL : https://patchwork.freedesktop.org/series/141974/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16171 -> Patchwork_141974v4
Summary
---
**FAILURE**
Seri
Hi Dave and Sima,
Here is the first drm-xe-next pull for 6.15. There are some additional
changes that we have in drm-xe-next that I decided to keep out for now
and also others that we should be merging early this week. I will see
how our CI goes with them before submitting second pull next week.
== Series Details ==
Series: LOBF enablement fix (rev4)
URL : https://patchwork.freedesktop.org/series/141974/
State : warning
== Summary ==
Error: dim checkpatch failed
cfe3cb6e3c2c drm/i915/lobf: Add lobf enablement in post plane update
15bce8901a81 drm/i915/lobf: Disintegrate alpm_disable f
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev10)
URL : https://patchwork.freedesktop.org/series/134383/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16171 -> Patchwork_134383v10
Su
== Series Details ==
Series: drm/i915/gt: Add a delay to let engine resumes correctly
URL : https://patchwork.freedesktop.org/series/145327/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16171 -> Patchwork_145327v1
Summary
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev10)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/i
From: Ville Syrjälä
Add the bit definitions needed for POST_LT_ADJ sequence.
Signed-off-by: Ville Syrjälä
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index c413ef68f9a3..260948a8f550 100644
== Series Details ==
Series: drm/i915/hdcp: switch to guard and scoped guard for mutexes
URL : https://patchwork.freedesktop.org/series/145326/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16171 -> Patchwork_145326v1
Summa
From: Ville Syrjälä
The fault handler is supposed to return true when it
handles the fault. The pipeDMC and ATS handlers are
returning false instead which results in the
"unreported faults" WARN triggering when it shouldn't.
Fixes: f13011a7 ("drm/i915: Pimp display fault reporting")
Signed-o
From: Ville Syrjälä
Implement the POST_LT_ADJ_REQ sequence, which should be used
to further fine tune the link if TPS4 is not supported.
The POST_LT_ADJ_REQ sequence will be performed after
the normal link training has succeeded.
Only the final hop between the last LTTPR and DPRX will
perform th
From: Ville Syrjälä
Disable TPS4 in favor of POST_LT_ADJ_REQ for testing purposes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/
From: Ville Syrjälä
Everyone implements the .set_idle_link_train() hook now.
Just make it mandatory.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_dp_link_training.c| 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/displ
From: Ville Syrjälä
In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_dp_link_training.c | 18 +-
.../drm/i915/display/inte
From: Ville Syrjälä
All platforms are capable of explicitly transmitting the idle
pattern. Implement it for everyone (so far it as implemented
only for HSW+).
The immediate benefit is that we gain support for the
POST_LT_ADJ_REQ sequence for all platforms.
Another potential future use would be
From: Ville Syrjälä
Move intel_dp_training_pattern() upwards to avoid the forward
declaration for the POST_LT_ADJ_REQ stuff.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_dp_link_training.c | 112 +-
1 file changed, 54 insertions(+), 58 deletions(-)
diff --git a/
From: Ville Syrjälä
We are supposed to switch off the training pattern in DPCD before
we start transmitting the idle pattern. For LTTPRs we do that
correctly, but for the sink DPRX we only do this correctly
for some platforms.
On pre-HSW (where we don't implement the .set_idle_link_train()
hook)
From: Ville Syrjälä
Add small helpers (drm_dp_post_lt_adj_req_supported() and
drm_dp_post_lt_adj_req_in_progress()) to help with implementing
the POST_LT_ADJ_REQ sequence.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/display/drm_dp_helper.c | 8
include/drm/display/drm_dp_helper.h
From: Ville Syrjälä
Implement the POST_LT_ADJ_REQ sequence, which is supposed
to be used to further tune the link vswing/pre-emphasis
when TPS4 is not supported.
Unfortunately I don't have any displays/dongles that support
this so I wasn't able to test anything. Hopefully CI has
something...
Vi
Add fixed refresh rate mode in crtc_state dump.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 1 -
drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
3 files changed, 3 insertions(+)
== Series Details ==
Series: drm/i915/dp_mst: Fix encoder HW state readout for UHBR MST
URL : https://patchwork.freedesktop.org/series/145300/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16170 -> Patchwork_145300v1
Summar
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:34AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> gen8_check_faults() and xehp_check_faults() are nearly identical.
> Refactor the common bits into gen8_report_fault().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Andi Shyti
Thanks,
Andi
In the interest of limiting the display dependencies on i915 core
headers, split out i915_gtt_view_types.h from i915_vma_types.h, and only
include the new header from intel_display_types.h.
Reuse the new header from xe compat code too, failing build if partial
view is used in display code.
Side n
With the primary goal of removing #include "i915_vma.h" from
intel_display_types.h, move intel_plane_ggtt_offset() to a proper
function in intel_atomic_plane.c. This reveals tons of implicit
dependencies all over the place that we pulled in via i915_vma.h. Fix
the fallout.
Signed-off-by: Jani Niku
Some shuffling to reduce dependencies on i915 headers.
Jani Nikula (2):
drm/i915: relocate intel_plane_ggtt_offset() to intel_atomic_plane.c
drm/i915: split out i915_gtt_view_types.h from i915_vma_types.h
drivers/gpu/drm/i915/display/intel_acpi.c | 2 +
.../gpu/drm/i915/display/intel_at
Fix typo in a comment.
explaination -> explanation
Signed-off-by: Yuichiro Tsuji
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_su
On 24/01/2025 11:46, Jani Nikula wrote:
On Thu, 23 Jan 2025, Simona Vetter wrote:
On Thu, Jan 23, 2025 at 05:09:10PM +0200, Jani Nikula wrote:
The expectation is that the struct drm_device based logging helpers get
passed an actual struct drm_device pointer rather than some random
struct poi
v1: Initial version.
v2: Addressed review comments from Jani.
v3: Addressed review comments from Jouni.
v4: Addressed review comments received on v3.
Signed-off-by: Animesh Manna
Animesh Manna (8):
drm/i915/lobf: Add lobf enablement in post plane update
drm/i915/lobf: Disintegrate alpm_disab
Le 23/01/2025 à 16:09, Jani Nikula a écrit :
The expectation is that the struct drm_device based logging helpers get
passed an actual struct drm_device pointer rather than some random
struct pointer where you can dereference the ->dev member.
Convert drm_err(sched, ...) to dev_err(sched->dev,
Le 23/01/2025 à 16:09, Jani Nikula a écrit :
The expectation is that the struct drm_device based logging helpers get
passed an actual struct drm_device pointer rather than some random
struct pointer where you can dereference the ->dev member.
Add a static inline helper to convert struct drm_d
Le 23/01/2025 à 16:09, Jani Nikula a écrit :
The expectation is that the struct drm_device based logging helpers get
passed an actual struct drm_device pointer rather than some random
struct pointer where you can dereference the ->dev member.
Convert drm_err(hdmi, ...) to dev_err(hdmi->dev, .
On 20.02.2025 16:38, Matt Roper wrote:
> On pre-Xe2 platforms, one of the approaches to initialize the GT command
> streamer frequency is to use the display reference clock. That's no
> longer relevant from Xe2 onward (i.e., all of the platforms where Xe is
> officially supported). Furthermore, u
Do not program transcoder registers for VRR for the secondary pipe of
the joiner. Remove check to skip VRR for joiner case.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/
On 20.02.2025 16:38, Matt Roper wrote:
> The whole GT CS clock initialization area is poorly documented in the
> specs and a lot of this code seems to have been inherited from the
> Windows driver team long ago. There's nothing in the specs that
> specifically explains using the display reference
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:32AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The RING_FAULT bits have change a bit over the years. Document
> which platforms use which bits.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Andi Shyti
Thanks,
Andi
Lobf is enabled part of ALPM configuration and if has_lobf
is set to true respective bit for LOBF will be set. Add debug
print while setting the bitfield of LOBF.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
To have fixed refresh rate with VRR timing generator the
guardband/pipeline full can't be programmed on the fly. So we need to
ensure that the values satisfy both the fixed and variable refresh
rates.
Since we compute these value based on vmin, lets set the vmin to
crtc_vtotal for both fixed and v
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 19, 2025 2:29 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org
> Subject: [PATCH 3/4] drm/i915/dsb: Allow DSB based commits when scalers are in
> use
>
> From: Vi
For fixed refresh rate use fixed timings for all platforms that support
VRR. For this add checks to avoid computing and reading VRR for
platforms that do not support VRR.
For platforms that do support VRR, readback vrr timings whether or not
VRR_CTL_FLIP_LINE_EN is set in VRR_CTL or not.
Signed-of
MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate.
Currently for link training we depend on flipline to decide whether we
want to ignore the msa timings. With fixed refresh rate we will still
fill the flipline in all cases whether panel supports VRR or not.
C
The ALPM_CTL can be updated from different context, so
add mutex to sychonize the update.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 19 +--
drivers/gpu/drm/i915/display/intel_alpm.h | 6 --
drivers/gpu/drm/i915/display/intel_ddi.c
Switching between variable and fixed timings is possible as for that we
just need to flip between VRR timings. However for CMRR along with the
timings, few other bits also need to be changed on the fly, which might
cause issues. So disable CMRR for now, till we have variable and fixed
timings sorte
Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
generator is used with variable timings.
Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
when vmax == vmin == flipline (fixed refresh rate timing).
v2: Use intel_vrr_vmin_flipline() to account f
Enablement of LOBF is added in post plane update whenever
has_lobf flag is set. As LOBF can be enabled in non-psr
case as well so adding in post plane update. There is no
change of configuring alpm with psr path.
v1: Initial version.
v2: Use encoder-mask to find the associated encoder from
crtc-st
The comment about fixed average vtotal is incorrect.
Remove it.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index cac4931902
On 2/24/2025 11:47 AM, Ankit Nautiyal wrote:
Do not program transcoder registers for VRR for the secondary pipe of
the joiner. Remove check to skip VRR for joiner case.
Missed to drop this patch as mentioned in the last version.
Will work on this after the other changes are agreed upon, so t
LOBF can be enabled with vrr fixed rate mode, so add check
if vmin = vmax = flipline in compute_config().
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/dr
Add support for using VRR Timing generator for HDMI panels.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/inte
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:40AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We customarily define the bits of a register in big endian
> order. Reorder the gen9+ timestamp freq register bits to match.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Andi Shyti
Thanks,
An
On Mon, 24 Feb 2025, Animesh Manna wrote:
> Currently clearing of alpm registers is done through psr_disable()
> which is always not correct, without psr also alpm can exist. So
> dis-integrate alpm_disable() from psr_disable().
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/displ
On Mon, 24 Feb 2025, Animesh Manna wrote:
> For every commit the dependent condition for LOBF is checked
> and accordingly update has_lobf flag which will be used
> to update the ALPM_CTL register during commit.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c |
Add an interface in debugfs which will help in debugging LOBF
feature.
v1: Initial version.
v2:
- Remove FORCE_EN flag. [Jouni]
- Change prefix from I915 to INTEL. [Jani]
- Use u8 instead of bool for lobf-debug flag. [Jani]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alp
On Mon, 24 Feb 2025, Imre Deak wrote:
> The encoder HW/SW state verification should use a SW state which stays
> unchanged while the encoder/output is active. The intel_dp::is_mst flag
> used during state computation to choose between the DP SST/MST modes can
> change while the output is active, i
Make helpers to compute vmin and vmax.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 39 +++-
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
ind
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now always programs fixed timings.
Later if vrr timings are required, vrr_enable() will switch
to the real VRR timings.
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:35AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Convert the CHV EU/slice fuse bits to the modern REG_BIT()/etc.
> style.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Andi Shyti
Thanks,
Andi
Currently clearing of alpm registers is done through psr_disable()
which is always not correct, without psr also alpm can exist. So
dis-integrate alpm_disable() from psr_disable().
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 21 +++
drivers/gp
Separate out functions for computing cmrr and vrr timings.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++-
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/di
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:33AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add a proper bitmask definition for the pre-bdw fault
> virtual address bits insted of abusing PAGE_MASK.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Andi Shyti
Thanks,
Andi
Sometimes engine reset fails because the engine resumes from an
incorrect RING_HEAD. Engine head failed to set to zero even after
writing into it. This is a timing issue and we experimented
different values and found out that 20ms delay works best based
on testing.
So, add a 20ms delay to let engi
On Thu, 20 Feb 2025, Matt Roper wrote:
> There's cdclk-specific code to obtain the display reference clock,
> either by reading a strap register, or by using a platform-specific
> hardcoded value. There's at least one other place in our drivers that
> potentially needs this clock frequency, so re
For platforms for which vrr timing generator is always set, VRR_CTL
enable bit does not need to toggle, so modify the vrr_{enable/disable}
for this.
At the moment the helper intel_vrr_always_use_vrr_tg() return false for
all cases. This will be set later when all other bits are in place.
Signed-of
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all val
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
> style.
using REG_BIT() and co. doesn't alway make it more readable. In
some of the cases below I would have preferred not to use
scoped_guard() and guard() provide automatic unlocking for locks, with
cleaner function return paths for both happy and rainy day
scenarios. Switch HDCP over as a first experiment for i915 display.
Leave intel_hdcp_disable() be for now, as two nested scoped guards are a
bit much, but also can't us
Currently VRR timing generator is used only when VRR is enabled by
userspace for sinks that support VRR. From MTL+ gradually move away from
the older timing generator and use VRR timing generator for both variable
and fixed timings.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/
As per bspec 49268: Disable PSR before disabling VRR.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.
Configure VRR timing generator for DP MST for fixed refresh rate.
Currently the variable timings are supported only for DP and eDP and not
for DP MST. Call intel_vrr_compute_config for MST which will configure
fixed refresh rate timings irrespective of whether VRR is supported or
not.
Signed-off-b
Disable LOBF/ALPM for any erroneous condition from sink side.
v1: Initial version.
v2: Add centralized alpm error handling. [Jouni]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 25 +++
drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
drivers/
Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timin
To have Guardband/Pipeline_full reconfigured seamlessly, move the
guardband and pipeline_full checks out from the pure !fastset block in
intel_pipe_config_compare().
Update the intel_set_transcoder_timings_lrr() function to use
fixed refresh rate timings for platforms which always use
VRR timing ge
Currently we always compute the timings as if vrr is enabled.
With this approach the state checker becomes complicated when we
introduce fixed refresh rate mode with vrr timing generator.
To avoid the complications, instead of always computing vrr timings, we
compute vrr timings based on uapi.vrr_
On Fri, 21 Feb 2025, gareth...@intel.com wrote:
> From: Gareth Yu
>
> The condition change is because Gen 14 begins to support DSC 1.2
> and need to check if the sink supports DSC1.2
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13719
>
> Cc: Suraj Kandpal
> Cc: Juha-Pekka H
For every commit the dependent condition for LOBF is checked
and accordingly update has_lobf flag which will be used
to update the ALPM_CTL register during commit.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 16
drivers/gpu/drm/i915/display/intel
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