[PATCH 4/9] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c  | 18 +++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.h  |  2 +-
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index b2fb641e4e96..2506996bf16d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -489,12 +489,13 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp 
*intel_dp,
        _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
        _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
 
-void
+bool
 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
                          const struct intel_crtc_state *crtc_state,
                          enum drm_dp_phy dp_phy,
                          const u8 link_status[DP_LINK_STATUS_SIZE])
 {
+       bool changed = false;
        int lane;
 
        if (intel_dp_is_uhbr(crtc_state)) {
@@ -513,10 +514,17 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
                       TRAIN_REQ_PREEMPH_ARGS(link_status));
        }
 
-       for (lane = 0; lane < 4; lane++)
-               intel_dp->train_set[lane] =
-                       intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
-                                                      dp_phy, link_status, 
lane);
+       for (lane = 0; lane < 4; lane++) {
+               u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
+                                                       dp_phy, link_status, 
lane);
+               if (intel_dp->train_set[lane] == new)
+                       continue;
+
+               intel_dp->train_set[lane] = new;
+               changed = true;
+       }
+
+       return changed;
 }
 
 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h 
b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 46614124569f..1ba22ed6db08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -23,7 +23,7 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
                                   int link_bw, int rate_select, int lane_count,
                                   bool enhanced_framing);
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
                               const struct intel_crtc_state *crtc_state,
                               enum drm_dp_phy dp_phy,
                               const u8 link_status[DP_LINK_STATUS_SIZE]);
-- 
2.45.3