On Wed, Jan 29, 2025 at 07:19:37PM +, Al Viro wrote:
> On Wed, Jan 29, 2025 at 08:13:02AM +0100, Greg Kroah-Hartman wrote:
>
> > > Both are needed, actually. Slightly longer term I would rather
> > > split full_proxy_{read,write,lseek}() into short and full variant,
> > > getting rid of the "
On 1/30/2025 10:46 AM, Mitul Golani wrote:
as_sdp param changes from vrr to cmrr should happen to fastset.
Changing as_sdp params should not trigger any modeset.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file
On 1/30/2025 10:46 AM, Mitul Golani wrote:
Adaptive sync sdp param computation, we can configure during
full modeset as well when sink is having vrr support, where
it doesn't need dependency on vrr.enable status and can also
match vrr enable/disable fastset requirement.
--v2:
- Separate the
== Series Details ==
Series: Add AS_SDP to fastset (rev5)
URL : https://patchwork.freedesktop.org/series/137035/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16041 -> Patchwork_137035v5
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Add AS_SDP to fastset (rev5)
URL : https://patchwork.freedesktop.org/series/137035/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warnin
Compute as_sdp.vtotal based on minimum vtotal calculated
during vrr computation.
--v2:
- make a separate patch and update to vmin only [Ankit].
--v3:
- Update vtotal to vmin for cmrr case as well [Ankit].
--v4:
- update vtotal with wrapper function of vmin [Ville]
Signed-off-by: Mitul Golani
vrr.vsync_{start,end} computation should not depend on
crtc_state->vrr.enable.
--v1:
- Explain commit message more clearly [Jani]
- Instead of tweaking to fastset use vrr.flipline while computing AS_SDP.
--v2:
- Correct computation of vrr.vsync_start/end should not depend on
vrr.enable.[vill
Add crtc_state dump for vrr.vsync_{start/end} params to track the
state correctly.
--v2:
- remove vrr_ pretext and use space instead of underscore (Jani).
--v3:
- Rebase to latest drm-tip.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_stat
as_sdp param changes from vrr to cmrr should happen to fastset.
Changing as_sdp params should not trigger any modeset.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
Adaptive sync sdp param computation, we can configure during
full modeset as well when sink is having vrr support, where
it doesn't need dependency on vrr.enable status and can also
match vrr enable/disable fastset requirement.
--v2:
- Separate the change from as_sdp.vtotal. [Ankit]
Signed-off-b
From: Ankit Nautiyal
Currently we support Adaptive sync operation mode with dynamic frame
rate, but instead the operation mode with fixed rate is set.
This was initially set correctly in the earlier version of changes but
later got changed, while defining a macro for the same.
Fixes: a5bd5991cb8
vrr enable disable should happen with fastset, where
adptive sync SDP should not block it to full modeset.
Ankit Nautiyal (1):
drm/i915/dp: fix the Adaptive sync Operation mode for SDP
Mitul Golani (5):
drm/i915/vrr: Add crtc_state dump for vrr.vsync params
drm/i915/vrr: Compute vrr.vsync_{
On Wed, Jan 01, 2025 at 05:39:21PM +0200, Alexander Usyskin wrote:
> Enable runtime PM in mtd driver to notify graphics driver that
> whole card should be kept awake while nvm operations are
> performed through this driver.
>
> CC: Lucas De Marchi
> Acked-by: Miquel Raynal
> Signed-off-by: Alexa
On 1/27/2025 3:30 PM, Lucas De Marchi wrote:
On Mon, Jan 27, 2025 at 02:33:00PM -0800, Vinay Belgaumkar wrote:
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by:
On Wed, Jan 01, 2025 at 05:39:24PM +0200, Alexander Usyskin wrote:
> Enable access to internal non-volatile memory on DGFX
> with GSC/CSC devices via a child device.
> The nvm child device is exposed via auxiliary bus.
>
> Reviewed-by: Rodrigo Vivi
Since this patch needs a rebase anyway, please
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling
URL : https://patchwork.freedesktop.org/series/144122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16041 -> Patchwork_144122v1
Summary
--
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling
URL : https://patchwork.freedesktop.org/series/144122/
State : warning
== Summary ==
Error: dim checkpatch failed
393239b4a930 drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
72f7abf7639f drm/i915/ddi:
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling
URL : https://patchwork.freedesktop.org/series/144122/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/
On Wed, Jan 29, 2025 at 08:53:37PM -, Patchwork wrote:
> == Series Details ==
>
> Series: Regression on linux-next (next-20250120) (rev2)
> URL : https://patchwork.freedesktop.org/series/143978/
> State : failure
>
> == Summary ==
>
> Error: patch
> https://patchwork.freedesktop.org/api/1
== Series Details ==
Series: Regression on linux-next (next-20250120) (rev2)
URL : https://patchwork.freedesktop.org/series/143978/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/143978/revisions/2/mbox/ not
applied
Applying: Regression on linux-n
In the past intel_digital_port::dp.prepare_link_retrain() could be
called directly (vs. from a modeset) to retrain an enabled link. In that
case the port had to be first disabled and then re-enabled. That changed
with commit 2885d283cce5 ("drm/i915/dp: Retrain SST links via a modeset
commit"), afte
This patchset fixes two issues (in patch 2 and 4) and simplifies a few
other things in the DDI port enabling/disabling sequences. I noticed
these while thinking about a way to enable/disable ports as part of
the HW readout/sanitization, for which this patchset is also a
preparation.
Imre Deak (17)
From: Imre Deak
Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.
Bspec: 7534, 49533
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 21
Reuse the existing helper to compute the configuration value of the
XELPDP_PORT_BUF_CTL1 register for HDMI outputs instead of open-coding
this.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff
From: Imre Deak
The various flags in DDI_BUF_CTL must be programmed at different places
during a modeset. The expected value of the register at any moment is
cached in the intel_dp::DP variable and the whole register is written
using this variable. A simpler way would be not maintaining the cache
The functions disabling a port for MTL+ and earlier platforms only
differ by an extra step on MTL+ (to disable the D2D link) and the point
at which the port's idle state is waited for. Combine the two functions
accounting for the above differences, removing the duplication.
Signed-off-by: Imre Dea
Factor out a function to get the configuration fields in the DDI_BUF_CTL
register. This can be used for configuring an HDMI output as well.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32
1 file changed, 21 insertions(+), 11 deletions(-)
diff
The functions enabling a port (as part of link training) for MTL+ and
earlier platforms only differ by extra steps on MTL+:
- enable the D2D link
- set the link parameters
- configure the PORT_BUF_CTL1 register
and an extra step on earlier platforms:
- apply an ADLP TypeC workaround
All the extra
From: Imre Deak
The prefix of adlp_tbt_to_dp_alt_switch_wa() function name shows already
what is the relevant platform and encoder type/mode, so the
corresponding checks are a detail that can be hidden in the
function, do so.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.
Add a helper to enable a port instead of open-coding it.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++-
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/i
From: Imre Deak
Align the DDI_BUF_CTL register flag definitions with how this is done
elsewhere.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/g
Reuse the existing helper to compute the configuration value of the
DDI_BUF_CTL register for HDMI outputs instead of open-coding this.
Note that dropping the XE2LPD_DDI_BUF_D2D_LINK_ENABLE flag is ok,
since an earlier mtl_ddi_enable_d2d() has set it already and
intel_enable_ddi_buf()'s RMW will no
The prefix of the mtl_ddi_enable_d2d() / mtl_ddi_disable_d2d_link()
names show already what are the relevant platforms, so the corresponding
platform check is a detail that can be hidden in the functions, do so.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +++--
Make the PORT_WIDTH macro of the XELPDP_PORT_CTL1 register work the same
way as those used for the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL
registers: accept a width parameter and convert it to the given
register's encoding.
Signed-off-by: Imre Deak
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.
When waiting for a port to idle, there is no point in distinguishing the
platform specific timeouts, instead of just using the maximum timeout.
Simplify things accordingly, describing the Bspec platform specific
timeouts in code comments.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display
A port can be disabled only via a modeset (or during HW state
sanitization) when the port is enabled. Thus it's not required to check
the port's enabled state before disabling it. In any case if the port
happened to be disabled, the following disabling would be just a nop and
waiting for the buffer
From: Imre Deak
Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
where this had an off-by-one error.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(
The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.
Signed-off-by: Imre
On Wed, Jan 29, 2025 at 08:13:02AM +0100, Greg Kroah-Hartman wrote:
> > Both are needed, actually. Slightly longer term I would rather
> > split full_proxy_{read,write,lseek}() into short and full variant,
> > getting rid of the "check which pointer is non-NULL" and killed
> > the two remaining u
== Series Details ==
Series: drm/i915: DP and DP MST cleanups
URL : https://patchwork.freedesktop.org/series/144107/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16039 -> Patchwork_144107v1
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: DP and DP MST cleanups
URL : https://patchwork.freedesktop.org/series/144107/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: wa
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state
URL : https://patchwork.freedesktop.org/series/144102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16039 -> Patchwork_144102v1
Summary
On Wed, Jan 29, 2025 at 10:44 AM Tvrtko Ursulin wrote:
>
>
> On 28/01/2025 15:55, Juha-Pekka Heikkilä wrote:
> > On Tue, Jan 28, 2025 at 3:08 PM Tvrtko Ursulin wrote:
> >>
> >>
> >> Hi,
> >>
> >> On 05/03/2024 16:44, Jani Nikula wrote:
> >>> On Wed, 28 Feb 2024, Juha-Pekka Heikkila
> >>> wrote:
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state
URL : https://patchwork.freedesktop.org/series/144102/
State : warning
== Summary ==
Error: dim checkpatch failed
74a393b566c5 drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:53: WARNING:LON
Just some cleanup prep work to make future changes easier to manage.
Jani Nikula (6):
drm/i915/dp: constify struct link_config_limits pointers
drm/i915/dp: change the order of intel_dp_mtp_tu_compute_config()
params
drm/i915/mst: change where lane_count and port_clock are set
drm/i915/
Improve code clarity by using existing min_array() and max_array()
helpers to find the lowest and highest values in an array.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/
mst_stream_find_vcpi_slots_for_bpp() has become a thin wrapper that
merely juggles parameters around. Remove it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 ++---
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i
Move mst_state->pbn_div calculation to intel_dp_mtp_tu_compute_config()
to allow further refactoring.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 31 ++---
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
Semantically mst_stream_find_vcpi_slots_for_bpp() does not seem like the
place to make decisions about lane_count and port_clock. Move them to
the callers, and remove the limits parameter that becomes unused.
This leads to slight duplication, but a) this makes further refactoring
easier, and b) al
Pointers first, bpp params in min, max, step. This is slightly more
natural to follow.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 +++-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 +--
3 files changed
The limits get passed around, but are only modified in a few
places. Constify the pointers elsewhere so it's easier to follow where
they can be modified.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
drivers/gpu/drm/i915/display/intel_dp.h
On Wed, 29 Jan 2025, Mika Kahola wrote:
> The dedicated display PHYs reset to a power state that blocks S0ix,
> increasing idle system power. After a system reset (cold boot,
> S3/4/5, warm reset) if a dedicated PHY is not being brought up
> shortly, use these steps to move the PHY to the lowest p
On Wed, 29 Jan 2025, Mika Kahola wrote:
> For PLL programming for C10 and C20 we don't need to
> carry crtc_state but instead use only necessary parts
> of the crtc_state i.e. pll_state.
This is not a good enough justification alone. Usually we pass
crtc_state around because we're going to need m
On Tue, Jan 28, 2025 at 08:54:10AM +, MARDI Youness wrote:
>Hello,
>
>
>
>
nit: In drm/sched, we start with an upper case -> "drm/sched: Stop […]"
On Fri, 2025-01-24 at 13:46 +0200, Jani Nikula wrote:
> On Thu, 23 Jan 2025, Simona Vetter wrote:
> > On Thu, Jan 23, 2025 at 05:09:10PM +0200, Jani Nikula wrote:
> > > The expectation is that the struct drm_device based logg
Hello,
Could you help us on this issue:
https://github.com/intel/linux-intel-lts/issues/54
Host environment
Operating system: Gentoo Base System release 2.14
OS/kernel version:
https://github.com/intel/linux-intel-lts/tree/lts-v6.6.34-linux-240626T131354Z
Architecture: x86_64
QEMU flavor: qemu
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
For PLL programming for C10 and C20 we don't need to
carry crtc_state but instead use only necessary parts
of the crtc_state i.e. pll_state.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 109 +++
1 file changed, 64 insertions(+), 45 deletions(-)
d
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, December 20, 2024 2:35 PM
> To: Garg, Nemesa
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/display: After joiner compute pfit_dst
>
> On Thu, Dec 19, 2024 at 06:02:25P
Hi Mikolaj,
> > + if (!ppgtt->vm.allocate_va_range) {
> > + i915_vm_put(&ppgtt->vm);
> > + return 0;
> > + }
>
> I don't know if it feels more in line with kernel style, but consider
> changing it to a label before second `i915_vm_put` at end of function
> plus goto instea
On 1/28/2025 5:00 AM, Lucas De Marchi wrote:
On Mon, Jan 27, 2025 at 02:33:00PM -0800, Vinay Belgaumkar wrote:
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vi
On Tue, 2025-01-28 at 18:14 +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2025 at 05:54:15PM +0200, Vinod Govindapillai wrote:
> > Userspace can pass damage area clips per plane to track
> > changes in a plane and some display components can utilze
> > these damage clips for efficiently handling us
Hi Krzysztof
> + if (!ppgtt->vm.allocate_va_range) {
> + i915_vm_put(&ppgtt->vm);
> + return 0;
> + }
I don't know if it feels more in line with kernel style, but consider
changing it to a label before second `i915_vm_put` at end of function
plus goto instead of cr
On Tue, Jan 28, 2025 at 10:43:10AM -0500, Paul Moore wrote:
> On Tue, Jan 28, 2025 at 6:22 AM Joel Granados
> wrote:
> > On Mon, Jan 27, 2025 at 03:42:39PM +, Matthew Wilcox wrote:
> > > On Mon, Jan 27, 2025 at 04:55:58PM +0200, Jani Nikula wrote:
> > > > You could have static const within fu
Hi Krzysztof
> + if (!ppgtt->vm.allocate_va_range) {
> + i915_vm_put(&ppgtt->vm);
> + return 0;
> + }
I don't know if it feels more in line with kernel style, but consider
changing it to a label before second `i915_vm_put` at end of function
plus goto instead of cr
On 28/01/2025 15:55, Juha-Pekka Heikkilä wrote:
On Tue, Jan 28, 2025 at 3:08 PM Tvrtko Ursulin wrote:
Hi,
On 05/03/2024 16:44, Jani Nikula wrote:
On Wed, 28 Feb 2024, Juha-Pekka Heikkila wrote:
AuxCCS framebuffers don't work on Xe driver hence disable them
from plane capabilities until
On 16/01/2025 22:24, Lucas De Marchi wrote:
Since commit 4ba4f1afb6a9 ("perf: Generic hotplug support for a PMU with
a scope"), there's generic support for system-wide counters and
integration with cpu hotplug. Set our scope to PERF_PMU_SCOPE_SYS_WIDE
instead of all the boilerplate code for han
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