[PATCH 13/17] drm/i915/ddi: Factor out a helper to get DDI_BUF_CTL's config value

[Imre Deak]

Factor out a function to get the configuration fields in the DDI_BUF_CTL
register. This can be used for configuring an HDMI output as well.

Signed-off-by: Imre Deak <imre.d...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++++++++++++++++--------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 64c42505f2ad6..dd8ae5cf96c70 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -333,45 +333,55 @@ static int dp_phy_lane_stagger_delay(int port_clock)
        return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 
1000);
 }
 
-static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
-                                     const struct intel_crtc_state *crtc_state)
+static u32 intel_ddi_buf_ctl_config_val(struct intel_encoder *encoder,
+                                       const struct intel_crtc_state 
*crtc_state)
 {
        struct intel_display *display = to_intel_display(encoder);
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+       u32 val = 0;
 
        /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() 
later */
-       intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
+       val |= DDI_PORT_WIDTH(crtc_state->lane_count) |
                DDI_BUF_TRANS_SELECT(0);
 
        if (dig_port->lane_reversal)
-               intel_dp->DP |= DDI_BUF_PORT_REVERSAL;
+               val |= DDI_BUF_PORT_REVERSAL;
        if (dig_port->ddi_a_4_lanes)
-               intel_dp->DP |= DDI_A_4_LANES;
+               val |= DDI_A_4_LANES;
 
        if (DISPLAY_VER(i915) >= 14) {
                if (intel_dp_is_uhbr(crtc_state))
-                       intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+                       val |= DDI_BUF_PORT_DATA_40BIT;
                else
-                       intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+                       val |= DDI_BUF_PORT_DATA_10BIT;
        }
 
        if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) {
-               intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+               val |= ddi_buf_phy_link_rate(crtc_state->port_clock);
                /*
                 * TODO: remove the following once DDI_BUF_CTL is updated via
                 * an RMW everywhere.
                 */
                if (!intel_tc_port_in_tbt_alt_mode(dig_port))
-                       intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+                       val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
        }
 
        if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
                int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
 
-               intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
+               val |= DDI_BUF_LANE_STAGGER_DELAY(delay);
        }
+
+       return val;
+}
+
+static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+                                     const struct intel_crtc_state *crtc_state)
+{
+       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+       intel_dp->DP = intel_ddi_buf_ctl_config_val(encoder, crtc_state);
 }
 
 static u32 intel_ddi_buf_ctl_config_mask(struct intel_encoder *encoder)
-- 
2.44.2