On Thu, 12 Dec 2019, Matt Roper wrote:
> On Thu, Dec 12, 2019 at 12:11:30PM +0300, Dan Carpenter wrote:
>> The "num_dtd" variable is the number of elements in the
>> generic_dtd->dtd[] array so the > needs to be >= to prevent reading one
>> element beyond the end of the array.
>>
>> Fixes: 33ef6d
On Thu, 12 Dec 2019, Matt Roper wrote:
> On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
>> struct skl_wm_level {
>> @@ -1215,6 +1210,8 @@ struct drm_i915_private {
>> bool distrust_bios_wm;
>> } wm;
>>
>> +u8 enabled_slices; /* GEN11 has configurable
On 12/12/2019 17.19, Chris Wilson wrote:
> Quoting Matthew Auld (2019-12-12 15:11:02)
>> On Thu, 12 Dec 2019 at 14:20, Chris Wilson wrote:
>>>
>>> Quoting Abdiel Janulgue (2019-12-12 11:34:38)
Fault handler to handle missing pages for lmem objects.
v3: Add get_vm_cpu_ops, iterate
On 19/12/12 01:34, Lucas De Marchi wrote:
> On Wed, Dec 11, 2019 at 11:35:21PM -0800, Venkata Sandeep Dhanalakota wrote:
> > We do not require to register the sysctl paths per instance,
> > so making registration global.
> >
> > v2: make sysctl path register and unregister function driver
> >s
== Series Details ==
Series: drm/i915/dsc: fixes for ICL DSI DSC (rev3)
URL : https://patchwork.freedesktop.org/series/70770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15716_full
Summary
---
On Fri, Nov 29, 2019 at 03:37:07PM +0200, Stanislav Lisovskiy wrote:
> Current DBuf slices update wasn't done in proper
> plane, especially its "post" part, which should
> disable those only once vblank had passed and
> all other changes are committed.
>
> v2: Fix to use dev_priv and intel_atomic_
On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
> Current consensus that it is redundant as
> we already have skl_ddb_values struct out there,
> also this struct contains only single member
> which makes it unnecessary.
>
> v2: As dirty_pipes soon going to be nuked away
>
== Series Details ==
Series: AUX power well fixes (rev4)
URL : https://patchwork.freedesktop.org/series/70857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15737
Summary
---
**SUCCESS**
No regre
On Fri, Dec 13, 2019 at 01:43:03AM +, Patchwork wrote:
> == Series Details ==
>
> Series: AUX power well fixes (rev3)
> URL : https://patchwork.freedesktop.org/series/70857/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15736
> =
On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> While clearing the Ports ync mode enable and master select bits
> we need to make sure that we perform a RMW for disable else
> it sets the other bits casuing unwanted sideeffects.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/int
On Thu, Dec 12, 2019 at 05:18:02PM -0800, Manasi Navare wrote:
> On Thu, Dec 12, 2019 at 04:32:32PM -0800, Matt Roper wrote:
> > On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > > In case of tiled displays, all the tiles are linke dto each other
> >
> > Minor typo on "linked to"
== Series Details ==
Series: AUX power well fixes (rev3)
URL : https://patchwork.freedesktop.org/series/70857/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15736
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: drm/i915/bios: fix off by one in parse_generic_dtd()
URL : https://patchwork.freedesktop.org/series/70820/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15714_full
Summary
Hello Jani,
On 2019-12-09 15:03, Jani Nikula wrote:
On Tue, 03 Dec 2019, Jani Nikula wrote:
Now that the fbops member of struct fb_info is const, we can start
making the ops const as well.
Cc: Miguel Ojeda Sandonis
Cc: Robin van der Gracht
Reviewed-by: Daniel Vetter
Reviewed-by: Miguel Oje
On Thu, Dec 12, 2019 at 04:32:32PM -0800, Matt Roper wrote:
> On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > In case of tiled displays, all the tiles are linke dto each other
>
> Minor typo on "linked to" here.
I will fix it
>
> > for transcoder port sync. So in intel_atomic
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Mark context->state vma as
active while pinned
URL : https://patchwork.freedesktop.org/series/70860/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15735
=
On Thu, Dec 12, 2019 at 05:03:07PM -0800, Matt Roper wrote:
> On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> > Add an extra check before making master slave assignments for tiled
> > displays to make sure we make these assignments only if all tiled
> > connectors are present. If n
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need to land first. (Lucas)
v3: Drop the combo phy assertion. I
On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> Add an extra check before making master slave assignments for tiled
> displays to make sure we make these assignments only if all tiled
> connectors are present. If not then initialize the state to defaults
> so it does a normal non t
== Series Details ==
Series: Some debugfs enhancements (rev2)
URL : https://patchwork.freedesktop.org/series/70658/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15733
Summary
---
**FAILURE**
Ser
On Thu, Dec 12, 2019 at 02:05:10PM -0800, Manasi Navare wrote:
> On Thu, Dec 12, 2019 at 09:18:48AM +0200, Jani Nikula wrote:
> > On Wed, 11 Dec 2019, Manasi Navare wrote:
> > > On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote:
> > >> ICL eDP and DSI transcoders have a DSC engine separa
== Series Details ==
Series: AUX power well fixes (rev2)
URL : https://patchwork.freedesktop.org/series/70857/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu
On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> In case of tiled displays, all the tiles are linke dto each other
Minor typo on "linked to" here.
> for transcoder port sync. So in intel_atomic_check() we need to make
> sure that we add all the tiles to the modeset and if one of t
== Series Details ==
Series: Some debugfs enhancements (rev2)
URL : https://patchwork.freedesktop.org/series/70658/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/rps: Add frequency translation helpers
Okay!
Commit: drm/i915/gt: Move power ma
== Series Details ==
Series: Some debugfs enhancements (rev2)
URL : https://patchwork.freedesktop.org/series/70658/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ca6dd2fcb636 drm/i915/rps: Add frequency translation helpers
1529bdcd2469 drm/i915/gt: Move power management debug f
== Series Details ==
Series: drm/i915/gt: Set vm again after MI_SET_CONTEXT (rev2)
URL : https://patchwork.freedesktop.org/series/70839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15732
Summary
---
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
ring->vma as active during execution if we want to include the rinbuffer
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i91
Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL. And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is actually necessary for this platform:
* EHL/JSL don't actually n
Matt Roper (3):
drm/i915/ehl: Define EHL powerwells independently of ICL
drm/i915/tgl: Drop Wa#1178
drm/i915/icl: Cleanup combo PHY aux power well handlers
.../drm/i915/display/intel_display_power.c| 176 --
drivers/gpu/drm/i915/i915_reg.h | 4 +-
2 files
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need to land first. (Lucas)
v3: Drop the combo phy assertion. I
The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it. In fact Swati just discovered that applying this workaround
is the root cause of some power well enable failures we've been seeing
in CI (gitlab issu
On Thu, Dec 12, 2019 at 03:56:38PM -0800, Lucas De Marchi wrote:
> On Thu, Dec 12, 2019 at 03:51:21PM -0800, Matt Roper wrote:
> > Now that the combo PHY aux power well handlers are used exclusively on
> > Icelake, we can drop a bunch of the extra tests.
> >
> > v2: Don't try to use intel_uncore_r
On Thu, Dec 12, 2019 at 03:51:21PM -0800, Matt Roper wrote:
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need
On Thu, Dec 12, 2019 at 02:37:34PM -0800, Matt Roper wrote:
The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it. In fact Swati just discovered that applying this workaround
is the root cause of some p
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Mark context->state vma as
active while pinned
URL : https://patchwork.freedesktop.org/series/70854/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15731
=
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need to land first. (Lucas)
Cc: Lucas De Marchi
Signed-off-by:
== Series Details ==
Series: series starting with [1/3] drm/i915: Use EAGAIN for trylock failures
(rev2)
URL : https://patchwork.freedesktop.org/series/70797/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15712_full
=
On 12/12/19 1:53 PM, Michal Wajdeczko wrote:
On Thu, 12 Dec 2019 01:23:33 +0100, Daniele Ceraolo Spurio
wrote:
On 12/10/19 12:47 PM, Michal Wajdeczko wrote:
Instead of spreading multiple conditionals across the uC code
to find out current mode of uC operation, start using predefined
set
On Thu, Dec 12, 2019 at 02:37:35PM -0800, Matt Roper wrote:
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests. While we're at it,
also switch these over to using intel_uncore_rmw() for the relevant
register updates.
display/
On 12/12/2019 18:43, Fernando Pacheco wrote:
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
We provide a minimal set of registers that should get things
working and extend as needed.
v2: rebase and comment to explain why
== Series Details ==
Series: drm/i915: opregion: set opregion chpd value to indicate the driver
handles hotplug (rev2)
URL : https://patchwork.freedesktop.org/series/69902/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554 -> Patchwork_15730
=
Quoting Sean Paul (2019-12-12 22:50:12)
> On Thu, Dec 12, 2019 at 4:34 PM Patchwork
> > Possible regressions
> >
> > * igt@gem_close_race@basic-threads:
> > - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2]
> >[1]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7553/fi-byt-j
On Thu, Dec 12, 2019 at 4:34 PM Patchwork
wrote:
>
> == Series Details ==
>
> Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev2)
> URL : https://patchwork.freedesktop.org/series/70393/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7553 -> Patchwork_1
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_rps_read_cagf: reads the frequency and returns it not
normalized
- intel_rps_read_actual_frequency: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-o
Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL. And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is actually necessary for this platform:
* EHL/JSL don't actually n
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests. While we're at it,
also switch these over to using intel_uncore_rmw() for the relevant
register updates.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
.../drm/i915/displa
The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it. In fact Swati just discovered that applying this workaround
is the root cause of some power well enable failures we've been seeing
in CI (gitlab issu
A few fixes related to AUX power wells for various platforms:
* EHL shouldn't use TC power well handling on C/D since all of its
outputs are combo.
* TGL shouldn't be applying Display WA #1178; doing so causes failures
to enable power wells in some cases.
There's some ambiguity as to wheth
== Series Details ==
Series: series starting with [1/2] drm/i915: panel: Use
intel_panel_compute_brightness() from pwm_setup_backlight()
URL : https://patchwork.freedesktop.org/series/70849/
State : failure
== Summary ==
Applying: drm/i915: panel: Use intel_panel_compute_brightness() from
pw
Reloading the PD after MI_SET_CONTEXT, along with copious amounts of
flushes, so far is making Baytrail more content.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 100 --
1 file changed, 45 insertions(+), 55 deletions(-)
diff --git a/drivers/gp
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile
From: Andi Shyti
Hi,
this two patches are few debugfs improvements. The first adds
some helpers for reading the GT frequency, while the second patch
moves all the power management debufs functions into gt/
Thanks,
Andi
Changelog:
==
v1-v2:
- renamed functions from
intel_cagf_f
Quoting Andi Shyti (2019-12-12 22:01:21)
> +static const struct drm_info_list i915_gt_pm_debugfs_list[] = {
> + {"i915_frequency_info", i915_frequency_info, 0},
> + {"i915_ring_freq_table", i915_ring_freq_table, 0},
> + {"i915_rps_boost_info", i915_rps_boost_info, 0},
> + {"
On Thu, Dec 12, 2019 at 09:18:48AM +0200, Jani Nikula wrote:
> On Wed, 11 Dec 2019, Manasi Navare wrote:
> > On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote:
> >> ICL eDP and DSI transcoders have a DSC engine separate from the
> >> pipe. Abstract the register selection and fix it for I
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
ring->vma as active during execution if we want to include the rinbuffer
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i91
On Thu, 12 Dec 2019 01:23:33 +0100, Daniele Ceraolo Spurio
wrote:
On 12/10/19 12:47 PM, Michal Wajdeczko wrote:
Instead of spreading multiple conditionals across the uC code
to find out current mode of uC operation, start using predefined
set of function pointers that reflect that mode.
B
Hi Jani.
On Tue, Dec 10, 2019 at 02:30:43PM +0200, Jani Nikula wrote:
> Add new struct drm_device based logging macros modeled after the core
> kernel device based logging macros. These would be preferred over the
> drm printk and struct device based macros in drm code, where possible.
>
> We hav
Quoting Lionel Landwerlin (2019-12-12 21:35:00)
> On 12/12/2019 21:55, Lionel Landwerlin wrote:
> > On 12/12/2019 16:04, Chris Wilson wrote:
> >> As we use the active state to keep the vma alive while we are reading
> >> its contents during GPU error capture, we need to mark the
> >> context->state
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gem: Prepare gen7 cmdparser for
async execution (rev2)
URL : https://patchwork.freedesktop.org/series/70793/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15711_full
===
On Thu, Dec 12, 2019 at 11:28:30PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 10:45:25AM -0800, José Roberto de Souza wrote:
> > Check if fastset is allowed by external dependencies like other pipes
> > and transcoders.
> >
> > Right now it only forces a fullmodeset when the MST master
On 12/12/2019 21:55, Lionel Landwerlin wrote:
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the er
On Wed, Dec 11, 2019 at 11:35:21PM -0800, Venkata Sandeep Dhanalakota wrote:
We do not require to register the sysctl paths per instance,
so making registration global.
v2: make sysctl path register and unregister function driver
specific (Tvrtko and Lucas).
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
== Series Details ==
Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev2)
URL : https://patchwork.freedesktop.org/series/70393/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7553 -> Patchwork_15728
Summary
On Wed, Dec 11, 2019 at 10:45:25AM -0800, José Roberto de Souza wrote:
> Check if fastset is allowed by external dependencies like other pipes
> and transcoders.
>
> Right now it only forces a fullmodeset when the MST master transcoder
> did not changed but the pipe of the master transcoder needs
The KBL failure does not look related to the changes in this patch series.
Tomi, could you confirm if this is a false negative?
Manasi
On Thu, Dec 12, 2019 at 02:46:49AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm: Handle connector tile support only
On Wed, Dec 11, 2019 at 10:45:23AM -0800, José Roberto de Souza wrote:
> Due to DDB overlaps the pipe enabling sequence is not always crescent.
> As the previous patch selects the smallest pipe/transcoder in the MST
> stream to be master and it needs to be enabled first this changes
> were needed t
On Thu, Dec 12, 2019 at 08:30:20AM +, Chris Wilson wrote:
Quoting Venkata Sandeep Dhanalakota (2019-12-12 07:35:22)
Adding device name to trace makes debugging easier,
when dealing with multiple gpus.
I'm not going to type that by hand, so let's try a little bit of
ingenuity.
---
drivers/
== Series Details ==
Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev2)
URL : https://patchwork.freedesktop.org/series/70393/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4f25d7348ece drm/i915: Fix sha_text population code
-:53: WARNING:LINE_SPACING: Missing
On 12/12/2019 20:38, Chris Wilson wrote:
> Quoting Colin Ian King (2019-12-12 19:53:33)
>> Hi,
>>
>> Static analysis with Coverity has picked up an issue with the following
>> commit:
>>
>> commit 65c29dbb19b2451990c5c477fef7ada3b8218f05
>> Author: Chris Wilson
>> Date: Wed Dec 11 15:02:04 2019
According to both the old acpi_igd_opregion_spec_0.pdf and the newer
skl_opregion_rev0p5.pdf opregion specification documents, if a driver
handles hotplug events itself, it should set the opregion CHPD field to
1 to indicate this and the firmware should respond to this by no longer
sending ACPI 0x0
On Wed, Dec 11, 2019 at 10:45:22AM -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port must
> send its stream to a master transcoder and master will send to DDI
> respecting the time
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Provide mmio list to be
saved/restored on engine reset
URL : https://patchwork.freedesktop.org/series/70844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7552 -> Patchwork_15727
===
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
(rev2)
URL : https://patchwork.freedesktop.org/series/70802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15710_full
==
Quoting Colin Ian King (2019-12-12 19:53:33)
> Hi,
>
> Static analysis with Coverity has picked up an issue with the following
> commit:
>
> commit 65c29dbb19b2451990c5c477fef7ada3b8218f05
> Author: Chris Wilson
> Date: Wed Dec 11 15:02:04 2019 +
>
> drm/i915: Use the i915_device name
On Thu, Dec 12, 2019 at 09:37:17AM -0800, Matt Roper wrote:
On Wed, Dec 11, 2019 at 04:22:50PM -0800, Lucas De Marchi wrote:
On Wed, Dec 11, 2019 at 12:10:41PM +0530, Bharadiya,Pankaj wrote:
> On Tue, Dec 10, 2019 at 09:57:39PM -0800, Lucas De Marchi wrote:
> > On Mon, Dec 09, 2019 at 08:09:02PM
The Thundersoft TST178 tablet uses a DSI panel with an external PWM
controller (as all DSI panels do). But unlike other DSI panels a duty-cycle
of 100% turns the backlight off and 0% sets it to maximum brightness.
I've checked the VBT and there is a BDB_LVDS_BACKLIGHT section, but
it does not set
Use intel_panel_compute_brightness() from pwm_setup_backlight() so that
we correctly take i915_modparams.invert_brightness and/or
QUIRK_INVERT_BRIGHTNESS into account when setting + getting the initial
brightness value.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c
On Tue, Dec 10, 2019 at 11:04:14PM +0800, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some PCI
> IDs were removed in BSpec for CML. This patch is used
> to eliminate the unsed ID.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
== Series Details ==
Series: drm/i915/gt: Set vm again after MI_SET_CONTEXT
URL : https://patchwork.freedesktop.org/series/70839/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7552 -> Patchwork_15726
Summary
---
**FA
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the error state.
Reported-by: Lionel Landwerlin
Fix
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
ring->vma as active during execution if we want to include the rinbuffer
in the error state.
Reported-by: Lionel Landwerlin
F
Hi,
Static analysis with Coverity has picked up an issue with the following
commit:
commit 65c29dbb19b2451990c5c477fef7ada3b8218f05
Author: Chris Wilson
Date: Wed Dec 11 15:02:04 2019 +
drm/i915: Use the i915_device name for identifying our request fences
In source drivers/gpu/drm/i9
== Series Details ==
Series: drm/i915: Set fence_work.ops before dma_fence_init
URL : https://patchwork.freedesktop.org/series/70837/
State : failure
== Summary ==
Applying: drm/i915: Set fence_work.ops before dma_fence_init
Using index info to reconstruct a base tree...
M drivers/gpu/dr
From: Sean Paul
This patch adds some protection against connectors being destroyed
before the HDCP workers are finished.
For check_work, we do a synchronous cancel after the connector is
unregistered which will ensure that it is finished before destruction.
In the case of prop_work, we can't do
From: Sean Paul
These functions are all the same for dp and dp_mst, so expose them for
use by the dp_mst hdcp implementation.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-11-s...@poorly.run
#v1
Changes in v2:
-none
---
.../drm/i915/displa
From: Sean Paul
Now that all the groundwork has been laid, we can turn on HDCP 1.4 over
MST. Everything except for toggling the HDCP signalling and HDCP 2.2
support is the same as the DP case, so we'll re-use those callbacks
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patc
Hi,
On 12-12-2019 16:52, Lee Jones wrote:
On Thu, 12 Dec 2019, Hans de Goede wrote:
Hi,
On 12-12-2019 09:45, Lee Jones wrote:
On Wed, 11 Dec 2019, Hans de Goede wrote:
Hi Lee,
On 10-12-2019 09:51, Lee Jones wrote:
On Tue, 19 Nov 2019, Hans de Goede wrote:
At least Bay Trail (BYT) and C
From: Sean Paul
In order to act upon content_protection property changes, we'll need to
implement the .update_pipe() hook. We can re-use intel_ddi_update_pipe
for this
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-10-s...@poorly.run
#v1
Cha
From: Sean Paul
Although DP_MST fake encoders are not subclassed from digital ports,
they are associated with them. Support these encoders.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-9-s...@poorly.run
#v1
Changes in v2:
-none
---
.../dr
From: Sean Paul
Instead of hand rolling the transfer ourselves in the hdcp hook, inspect
aux messages and add the aksv flag in the aux transfer hook.
IIRC, this was the original implementation and folks wanted this hack to
be isolated to the hdcp code, which makes sense.
However in testing an L
From: Sean Paul
This is a bit of housecleaning for a future patch. Instead of sprinkling
hdcp->value assignments and prop_work scheduling everywhere, introduce a
function to do it for us.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-7-s...@p
From: Sean Paul
This patch is required for HDCP over MST. If a port is being used for
multiple HDCP streams, we don't want to fully disable HDCP on a port if
one of them is disabled. Instead, we just disable the HDCP signalling on
that particular pipe and exit early. The last pipe to disable HDCP
From: Sean Paul
Instead of using intel_dig_port's encoder pipe to determine which
transcoder to toggle signalling on, use the cpu_transcoder field already
stored in intel_hdmi.
This is particularly important for MST.
Suggested-by: Ville Syrjälä
Signed-off-by: Sean Paul
Changes in v2:
- Added
From: Sean Paul
HDCP signalling should not be left on, WARN if it is
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Sean Paul
Changes in v2:
- Added to the set in lieu of just clearing the bit
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --g
From: Sean Paul
On HDCP disable, clear the repeater bit. This ensures if we connect a
non-repeater sink after a repeater, the bit is in the state we expect.
Fixes: ee5e5e7a5e0f ("drm/i915: Add HDCP framework + base implementation")
Cc: Chris Wilson
Cc: Ramalingam C
Cc: Daniel Vetter
Cc: Sean
From: Sean Paul
This patch fixes a few bugs:
1- We weren't taking into account sha_leftovers when adding multiple
ksvs to sha_text. As such, we were or'ing the end of ksv[j - 1] with
the beginning of ksv[j]
2- In the sha_leftovers == 2 and sha_leftovers == 3 case, bstatus was
being pla
From: Sean Paul
Hello again,
Here's the second version of my set to enable MST over HDCP. The big
changes stemmed from Ville's review. It was super helpful to get that
pushback, and led me to more critically debug the disable paths. As a
result, I think I chased a few more gremlins out of the sys
== Series Details ==
Series: drm/i915/display: Silence powerell debug
URL : https://patchwork.freedesktop.org/series/70836/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7551 -> Patchwork_15724
Summary
---
**FAILURE*
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