On Fri, Nov 29, 2019 at 03:37:07PM +0200, Stanislav Lisovskiy wrote:
> Current DBuf slices update wasn't done in proper
> plane, especially its "post" part, which should
> disable those only once vblank had passed and
> all other changes are committed.
>
> v2: Fix to use dev_priv and intel_atomic_state
> instead of skl_ddb_values
> (to be nuked in Villes patch)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++------
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index dda43e3dcdbf..db0830745f25 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14637,6 +14637,28 @@ static void
> intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
> state);
> }
>
> +static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + u8 hw_enabled_slices = dev_priv->enabled_slices;
> + u8 required_slices = state->enabled_slices;
> +
> + /* If 2nd DBuf slice required, enable it here */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +}
> +
> +static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + u8 hw_enabled_slices = dev_priv->enabled_slices;
> + u8 required_slices = state->enabled_slices;
> +
> + /* If 2nd DBuf slice is no more required disable it */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +}
> +
> static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -14645,8 +14667,6 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
> unsigned int updated = 0;
> bool progress;
> int i;
> - u8 hw_enabled_slices = dev_priv->enabled_slices;
> - u8 required_slices = state->enabled_slices;
> struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i)
> @@ -14654,10 +14674,6 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
> if (new_crtc_state->hw.active)
> entries[i] = old_crtc_state->wm.skl.ddb;
>
> - /* If 2nd DBuf slice required, enable it here */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> -
> /*
> * Whenever the number of active pipes changes, we need to make sure we
> * update the pipes in the right order so that their ddb allocations
> @@ -14714,10 +14730,6 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
> progress = true;
> }
> } while (progress);
> -
> - /* If 2nd DBuf slice is no more required disable it */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> }
>
> static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
> @@ -14847,6 +14859,9 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> if (state->modeset)
> intel_encoders_update_prepare(state);
>
> + /* Enable all new slices, we might need */
> + icl_dbuf_slice_pre_update(state);
> +
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display.commit_modeset_enables(state);
>
> @@ -14906,6 +14921,9 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> if (state->modeset && intel_can_enable_sagv(state))
> intel_enable_sagv(dev_priv);
>
> + /* Disable all slices, we don't need */
> + icl_dbuf_slice_post_update(state);
> +
> drm_atomic_helper_commit_hw_done(&state->base);
>
> if (state->modeset) {
> --
> 2.17.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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