On Tue, 27 Sep 2011 22:54:01 +0100
Chris Wilson wrote:
> On Tue, 27 Sep 2011 12:38:59 -0700, Ben Widawsky wrote:
> > If we do this we lose the possibility to kick rings, but not reset the
> > GPU (not that I find that terribly useful. If we do this, it does fire a
> > wq event, but I don't see a
On Tue, 27 Sep 2011 12:38:59 -0700, Ben Widawsky wrote:
> If we do this we lose the possibility to kick rings, but not reset the
> GPU (not that I find that terribly useful. If we do this, it does fire a
> wq event, but I don't see a problem with that for this case.
>
> I think I would rather do
On Tue, 27 Sep 2011 20:03:17 +0200
Daniel Vetter wrote:
> On Tue, Sep 27, 2011 at 06:31:59PM +0100, Chris Wilson wrote:
> > On Tue, 27 Sep 2011 09:46:14 -0700, Ben Widawsky wrote:
> > > On Tue, 27 Sep 2011 12:03:22 +0200
> > > Daniel Vetter wrote:
> > >
> > > > On Mon, Sep 26, 2011 at 10:22:01
On Tue, 27 Sep 2011 17:56:39 +0100, Chris Wilson
wrote:
> Ah, now I see why we moved from using the active configuration earlier. ;-)
My evil plan is revealed!
> Doesn't this prevent us from ever using SSC though, as virtually every
> single PCH machine has HDMI encoders that haven't been mask
On Tue, 27 Sep 2011 17:47:10 +0100, Chris Wilson
wrote:
> On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard wrote:
> > The PCH refclk settings are global, so we need to look at all of the
> > encoders, not just the current encoder when deciding how to configure
> > it. Also, handle systems with
On Tue, Sep 27, 2011 at 06:31:59PM +0100, Chris Wilson wrote:
> On Tue, 27 Sep 2011 09:46:14 -0700, Ben Widawsky wrote:
> > On Tue, 27 Sep 2011 12:03:22 +0200
> > Daniel Vetter wrote:
> >
> > > On Mon, Sep 26, 2011 at 10:22:01PM -0700, Ben Widawsky wrote:
> > > > On Mon, 26 Sep 2011 19:59:50 +02
On Tue, 27 Sep 2011 09:46:14 -0700, Ben Widawsky wrote:
> On Tue, 27 Sep 2011 12:03:22 +0200
> Daniel Vetter wrote:
>
> > On Mon, Sep 26, 2011 at 10:22:01PM -0700, Ben Widawsky wrote:
> > > On Mon, 26 Sep 2011 19:59:50 +0200
> > > Daniel Vetter wrote:
> > > > diff --git a/drivers/gpu/drm/i915/i
On Mon, 26 Sep 2011 23:11:46 -0700, Keith Packard wrote:
> The reference clock configuration must be done before any mode setting
> can occur as all outputs must be disabled to change
> anything. Initialize the clocks after turning everything off during
> the initialization process.
Ah, now I see
On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson
wrote:
> Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for
> any output other than DP_A. However, the configuration register marks that
> as being a test-only mode.
Ok, it's all irrelevant -- the only configurations using
On Mon, 26 Sep 2011 23:11:45 -0700, Keith Packard wrote:
> I can't find any reference clocks which run at 96MHz as seems to be
> indicated from the comments in this code.
>
> Signed-off-by: Keith Packard
I think there exists a 100MHz test mode (certainly there is reference to
such in the diagra
On Mon, 26 Sep 2011 23:11:44 -0700, Keith Packard wrote:
> This eliminates VGA shimmer on some Ironlake machines which have a
> CK505 clock source.
>
> Signed-off-by: Keith Packard
References: https://bugzilla.kernel.org/show_bug.cgi?id=21742
References: https://bugs.freedesktop.org/show_bug.cgi
On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard wrote:
> The PCH refclk settings are global, so we need to look at all of the
> encoders, not just the current encoder when deciding how to configure
> it. Also, handle systems with more than one panel (any combination of
> PCH/non-PCH eDP and LVDS
On Tue, 27 Sep 2011 12:03:22 +0200
Daniel Vetter wrote:
> On Mon, Sep 26, 2011 at 10:22:01PM -0700, Ben Widawsky wrote:
> > On Mon, 26 Sep 2011 19:59:50 +0200
> > Daniel Vetter wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index da5d607..09c11e
On Mon, 26 Sep 2011 23:11:42 -0700, Keith Packard wrote:
> Allow SSC to be enabled even when the BIOS disables it for testing SSC paths.
>
> Signed-off-by: Keith Packard
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_
On Mon, 26 Sep 2011 23:11:40 -0700, Keith Packard wrote:
> This tells the driver whether a CK505 clock source is available on
> pre-PCH hardware. If so, it should be used as the non-SSC source,
> leaving the internal clock for use as the SSC source.
>
> Signed-off-by: Keith Packard
Reviewed-by:
On Mon, 26 Sep 2011 23:11:39 -0700, Keith Packard wrote:
> These are all KMS related anyways, so don't hide them under other
> debug levels.
>
> Signed-off-by: Keith Packard
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_
On Mon, Sep 26, 2011 at 10:22:01PM -0700, Ben Widawsky wrote:
> On Mon, 26 Sep 2011 19:59:50 +0200
> Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c index da5d607..09c11e4 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers
On Mon, Sep 26, 2011 at 21:07, Andrew Lutomirski wrote:
> On Sep 26, 2011 9:00 PM, "Daniel Vetter" wrote:
>>
>> Only do it in the hope of resurrecting the gpu. Disable when reset is
>> disabled because it seems to tremendously increases our changes to
>> actually capture an error_state before the
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard wrote:
> Ok, so I'd love to know where in any PCH reference matter someone has
> found a place where the reference clock for any of the PLLs is
> anything other than 120MHz. Can someone find a reference for other
> frequencies?
Oddly in the diagr
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