On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for > any output other than DP_A. However, the configuration register marks that > as being a test-only mode. Ok, it's all irrelevant -- the only configurations using anything other than a fixed 120MHz were eDP and LVDS. LVDS used a value from the BIOS, which is presumably always 120MHz. eDP ignored the refclk and used fixed PLL values. So, yes, we can always set the refclk to 120MHz; the cases which matter were using that value already. -- keith.pack...@intel.com
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