It seems to be back now, but please let us know if you can't access it!
I think it was related to the Fastly outage. See the CNN article for more
details :).
https://www.cnn.com/2021/06/08/tech/internet-outage-fastly/index.html
Cheers,
Jason
On Tue, Jun 8, 2021 at 3:21 AM Pedro Henrique Exenber
Hi Patrick,
gem5 doesn't support multiple cache line sizes "out of the box", but
there's no reason you couldn't add the support. Creating a memory-side
cache with a larger cache line is certainly possible! You might need to
make some modifications to the Cache SimObject or create your own object.
Hi Sam,
No, there's not good documentation on this (yet ;)). It's relatively easy
to set up, though. Instead of using a single packet ptr, you can have a
queue (or whatever datastructure you would like), and you can set the
blocked flag only when it is "full" (e.g., the number of items in the
stru
Hi Deepak,
Have you tried the latest gem5? There's been a lot of work in both
gem5-21.0 and on gem5-develop to improve the RISC-V FS support. Another
option would be to look at how the RISC-V code has changed to see if that
helps diagnose this problem.
Cheers,
Jason
On Fri, Jun 18, 2021 at 10:29
Hi Deepak,
Yeah, the cache disable bit may not work correctly in the page table
walker/TLB. You can check the code there to see if that's what's going
wrong.
You can also try adding an E820 entry to the workload object (e.g.,
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable
Hi Pedro,
No, I don't think there's an easy way to run m5_write_file on the guest
from the host. That is an instruction that is executed on the guest, and
the host can't easily control what is executing on the guest (especially
when you consider that it has to execute in the right context, etc.).
Hi Xijing,
You can set specific mappings from virtual to physical addresses by calling
the `map()` function on the Process object from your python configuration
file. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/Process.py#37
Then, once you have a virtual->physical ma
Hi Sam,
Are the (virtual, physical?) addresses different when you use the larger
arrays? I wonder if the underlying mmap or malloc calls are breaking in SE
mode somehow. Maybe, after you allocate in your guest code you can print
out the virtual address to make sure it looks reasonable. You can als
Hi Vincent,
It depends on when/how you're ending the simulation. If you end the
simulation at some particular tick, then you'll see writes left in the
write queue. Just like a real machine, writes don't happen instantaneously,
and at some point in time, there are writes sitting in the write buffer
Hi everyone,
These details on gem5-resources have also been tested multiple times. We
have also gotten unmodified OpenSBI working with gem5 as well. Ayaz can
provide more details if you need.
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/riscv-fs/
Cheers,
Jason
On
What version of gem5 are you using? I believe gem5-20.0+ has the getdents
syscall implemented. I'm sure that 21.0 has the syscall implemented.
Whether you're using Ruby or classic caches it shouldn't make
any difference on whether the syscalls are implemented.
Cheers,
Jason
On Fri, Jun 25, 2021 a
Hi Adrian,
gem5 has support for AMD's GCN3 (compute) GPU in SE mode, and we're working
on merging both Vega support (AMD's newer GPU ISA) and full system support.
The status of these new features can be followed on Jira.
Here's documentation on the current GPU support:
http://www.gem5.org/documen
Hi Adrian,
The AMD GPU model has never been tested with Arm. I doubt the ROCm stack
will compile/work with any ISA other than x86, unfortunately.
For multi-GPU support see
http://www.gem5.org/2020/05/30/enabling-multi-gpu.html
Of course, multiple CPUs will work with no problem with or without GP
Hello,
It's somewhat possible. You can compile gem5 as a library (e.g., scons
build//libgem5-opt.so). However, gem5 *is a python
interpreter* and is configured via python scripts. Getting that to work
with an external program is "exciting". It's possible to get python
working, and there are other
Hello,
Unfortunately, I don't think gem5 is the right tool for this job. When you
run that command, gem5's embedded python interpreter is executing `se.py`.
There's not really a way to easily get around this. You could try to
compile gem5 without python (--without-python, IIRC), but then configuri
See https://gem5.atlassian.net/browse/GEM5-618
On Sat, Jul 3, 2021 at 5:23 PM lovline via gem5-users
wrote:
> Hi,
>We are working on an important project, and we want to use RSCV-V1.0
> vector instructions on Gem5.
>But we cann't find any features or codes about RSCV-V on Gem5.
>We s
Hi Sam,
My suggestion would be to use gdb. You can run gem5 in gdb and then use
ctrl-c to stop the execution and see where the program is getting stuck.
Also, enabling debug flags (or just good ole printf debugging) can also be
useful in these cases.
Another option with gdb would be to put breakp
To use hardware-accelerated virtualization (i.e., KVM) your host and guest
must have the same ISA (and the host must have virtualization extension).
Cheers,
Jason
On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:
> Dear gem5 community,
>
> I have
Hi Liyichao,
We welcome contributions to the gem5 resources! Currently, we have full
system resources available for x86 and one available for RISC-V. We don't
have any Arm resources available right now, but that's only because we
haven't had the time (or resources ;)) to get around to it. Again, w
Hi Sam,
This is a use case that I don't think we've thought about in the mainline
gem5. I think the easiest solution would be to add some custom Statistics
objects to track the info from the function you're interested in.
Cheers,
Jason
On Wed, Aug 11, 2021 at 10:59 AM Thomas, Samuel via gem5-use
Hello,
It should be X86 (capitol X) instead of x86. You can see the files in
gem5/build_opts for the different possibilities for default build variables.
Cheers,
Jason
On Thu, Sep 2, 2021 at 3:58 AM Sravani Sravanam 20PHD7041 via gem5-users <
gem5-users@gem5.org> wrote:
> sir,
> i am sravani s
Hi Sindhuja,
Yes, there is an expectation that valgrind causes a slowdown. Let me give
you a couple of suggestions.
1. Make sure you compile without tcmalloc (e.g., scons
build//gem5.opt --without-tcmalloc). Using tcmalloc will make
valgrind miss all allocations.
2. Use the suppressions file in u
Hi Sam,
Sorry for the frustration. Writing better documentation is always #2 on the
priority list :(.
I always tell people not to trust any of the "options" to fs.py and se.py.
Those scripts have gotten so far beyond "out of hand" at this point that
they are almost useless. They are trying to be
Hi Emil,
You can remove that check. However, you should note that the classic caches
aren't designed to support high-bandwidth operation. Also, this assert
triggering could be a sign that there's infinite queuing somewhere (which
is one reason why the classic caches aren't great for high bandwidth
Hi Sam,
I would *guess* it's the draining code getting stuck in an infinite loop.
The draining code calls "drain" on all SimObjects in the system, and they
do their thing. Then, the drain code asks all SimObjects if they're done
draining. If not, it starts over and calls drain on all objects again
Hi Xihui,
That's just a warning and you can safely ignore it. The most recent hotfix
release should remove this warning as well.
Cheers,
Jason
On Sun, Sep 19, 2021 at 10:02 PM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:
> Hello everyone：
>
> I am a beginner with GEM5.
> Ther
Hi Xihui,
The error is "died with "
I would guess you're out of memory or trying to compile too many files at
once. But, it could be many different problems. If it's an issue with
dependencies or your host, you can always use our docker images:
https://www.gem5.org/documentation/general_docs/buil
Hi Reiko,
The KVM CPU requires that the host platform supports KVM. Given that you're
using WSL, this means that you need to have nested virtualization enabled
and implemented on your WSL kernel.
https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_accele
he resources! Seems like quite a can of worms.It's almost
> looking like it could be easier to partition a computer for Linux and start
> over. Would you recommend that as an alternative?
>
> All th
>
> On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users <
Hi Ange,
If you're using SE mode, you may be able to augment the allocation code to
track the heap size. E.g.,
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/mem_state.cc#108
In fact, the MemState object tracks both the stack and the heap, so you can
get a lot of informatio
Hi Sampad,
Here is where m5_reset_stats is implemented in the simulator:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303
There are a large number of steps between when the guest code calls
m5_reset_stats and when the above function executes, but this shoul
Hi Ali,
Is your guest code 32-bit Arm? If so, I think this could be the problem in
SE mode: https://gem5.atlassian.net/browse/GEM5-1074
Cheers,
Jason
On Tue, Oct 5, 2021 at 7:45 AM Ali Ghandour via gem5-users <
gem5-users@gem5.org> wrote:
> In FS mode, full errror stack below:
>
> Traceback (mo
Hello,
Does the file configs/learning_gem5/part1/simple.py work for you? If so,
then there is probably a small mistake in your configuration script. If
this is the case, can you send your script (maybe off list)? I would like
to understand the problem and improve the error message.
Cheers,
Jason
I would suggest using DPRINTF instead of cout. It's possible that some
print statements aren't being flushed.
Jason
On Mon, Oct 11, 2021 at 7:16 AM Sampad Mohapatra wrote:
> Hi Jason,
>
> I have added a std::cout statement to the resetstats()'s body and I am
> calling m5_reset_stats from my GPU
Hi Reiko,
I would guess that it's a permission issue as well. Maybe, by default, when
booting the image it logs in as a regular user?
What I would do is not pass the rcS script and log in interactively with
the m5term (see util/term). Then, run the commands in the rcS file one at a
time manually
Hi Victor,
It's not super easy to access stats between SimObjects. I would suggest
computing any and all formulas after running the simulation, not during the
simulation loop.
You can either parse the stats.txt or use the new python stats interface (
https://gem5.googlesource.com/public/gem5/+/re
Hi Fengze,
No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
https://www.youtube.com/watch?v=XTIrVB
Hi Jose,
This is an interesting question! My quick suggestion would be to "hack" the
loader/page table to skip the mapping portion when loading the elf section.
I don't fully understand exactly what the underlying "problem" is. That
said, we may be able to solve it "correctly" by generally skippi
Hello,
For Arm, gem5 has SVE support and (some/most/all?) of the NEON
instructions. For x86, we support most 128-bit SIMD instructions, but very
few or no 256-bit or 512-bit SIMD instructions. I have heard of
forks/groups that have implemented many of the x86 vector instructions, and
I have heard
Hi Nitesh,
I don't think there's any good documentation. This may help with Arm SVE
support, but it's from a while ago. Things have changed since 2018.
https://community.arm.com/arm-research/b/articles/posts/simulating-the-arm-sve-with-gem5
On Fri, Oct 29, 2021 at 2:27 AM Nitesh Narayana GS
wrot
Hello,
The m5 magic operations (either via magic instructions or addresses) will
work with all CPU models.
Cheers,
Jason
On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users
wrote:
> Hi All:
>
> Does “m5 --addr 0x1001 exit” take effect in the O3 system?
>
>
> __
Hello,
Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board
in the components library. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py
I am working on the CHI protocol. I have a WIP changeset that I could
share
Hi Fengze,
Yeah, there's a lot of complicated and undocumented things you need to do
when initializing a CPU.
Here's a couple of pointers that may help. However, this code was written a
few years ago and is almost 4000 commits behind, so things have probably
changed since then!
Code: https://gith
Hi Abdelrahman,
I think you have the right approach. Is the simulation not exiting after
the warmup_inst instructions?
Cheers,
Jason
On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:
> Hello,
>
> I am trying to warm up my gem5 in order to train
You can call cpu.scheduleInstStop(, , )
So, you can set an initial instruction limit which will exit from the
simulate() call. Then, you can reset the stats and set a new instruction
limit with scheduleInstStop. Then, call simulate() again. When this second
simulate returns you can dump the stats.
Hi Brian,
A few quick thoughts:
1. x86 + classic cache + multicore is not supported. There is a changeset
on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303)
which may fix this, but it has not been tested widely.
2. SE mode + pthreads will likely not work in all circumstances. T
Hi Brian,
You can try the patch linked below if you want x86 + multicore + classic.
There is a download button on that page. However, this isn't "officially"
supported.
Some Ruby protocols have been tested with x86 and multiple cores. The
details on the gem5-resources website and/or repo should d
Hi Elliot,
You may be able to get some inspiration from the code in gem5/ext/*. This
is where we have included external libraries.
Cheers,
Jason
On Fri, Dec 17, 2021 at 6:21 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:
>
> I have an external library that I would like to link with
Hi Fu,
You can modify that file to import a Ruby-based cache hierarchy (e.g.,
MESI_Two_Level and MI_Example have been tested). Or, better yet, create
your own run script. `riscv_fs.py` is just an *example* of how to use the
standard library components.
Cheers,
Jason
On Fri, Dec 24, 2021 at 7:57
Hello,
If you are using *atomic* memory mode, then the tick number is mostly
ignored. If you're using *timing* mode, then the tick number should be used
by whatever object calls the read/write function and the delay is inserted
there. Also, if your program doesn't have a direct dependence on the I
Hi Sam,
I was wondering when this problem would come up again. Here's a Jira issue
to track the same thing in a different context:
https://gem5.atlassian.net/browse/GEM5-1003
Could you do something like `du -h build/ | sort -h` to see what objects
are the biggest? I'm going to guess that there ar
Good question, Felix!
The short answer is that since there are instructions that take multiple
cycles to execute you need something like a scoreboard to track the
dependencies.
In the H&P book, you can see some details of this in Appendix C.5 (6th
edition). If you happen to have the Patterson and
Namespaces were recently added to gem5 and the documentation hasn't been
updated, yet. We'll put that on the to do list.
Cheers,
Jason
On Wed, Feb 2, 2022 at 6:11 AM Zhang Zhiyuan via gem5-users <
gem5-users@gem5.org> wrote:
> Dear gem5 faculties:
>
> Hi! I’ve been trying to follow the getting s
Hi Scott,
If you want something to execute before gem5 is completed, you can call
`registerExitCallback`. See
http://doxygen.gem5.org/release/current/namespacegem5.html#abcf3056836ee522620e5b14d9392ea87
I *think* that will solve your problem, but let me know if not. I don't
think there's a clean
Hi Scott,
I think the answer is the same as the prior email. You need to register an
exit callback to close the file stream :). See, for instance, the elastic
trace code:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/cpu/o3/probe/elastic_trace.cc#103
Cheers,
Jason
On Wed, Feb
Hi Uma,
Not all X86 vector instructions are implemented. What you're seeing is
that pmovzxbw isn't
implemented. Specifically, there's at least one version (as shown here
https://www.felixcloutier.com/x86/pmovzx) which hasn't been implemented
yet. I'm not sure which one. The `Vdq_Udq_or_Mq` somehow
Hello,
This specific setup has not been tested, as far as I know. I would also
suggest using v21.2.1 as there have been lots of bugfixes to CHI in the
past year.
Cheers,
Jason
On Tue, Feb 15, 2022 at 6:23 PM Liyichao via gem5-users
wrote:
> Hi All:
>
> Does the gem5 v21.0.1.0 support
Hi David,
Sorry for the confusion. We need to update that documentation! You can now
find the script here:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/example/gem5_library/x86-npb-benchmarks.py
(or in configs/example/gem5_library in the gem5 repo).
Cheers,
Jason
On Thu,
Hi Jianda,
There will also be a tutorial and workshop at ISCA in New York this year
(June 11). More info coming soon!
Cheers,
Jason
On Fri, Feb 18, 2022 at 8:21 AM Gabriel Busnot via gem5-users <
gem5-users@gem5.org> wrote:
> Hi and welcome Jianda,
>
> You are in the right place! Feel free to s
Hi George,
For workbegin/workend, they can be called from within applications if you
link to the libm5 library. For instance, in the parsec resource here:
https://resources.gem5.org/resources/parsec we use the m5_workbegin()
function in the ROI hooks. See
https://gem5.googlesource.com/public/gem5-
inary in FS mode.
> Note that I'm running first in KVM mode on a x86 host hoping to switch CPUs
> once the work start event happens. Are magic ops unsupported in KVM mode?
>
> Thanks!
>
>
> On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via
> gem5-users wrote
Hi Abdelrahman,
>From the get error message, it says:
"This error may be caused by a too restrictive setting
in the file '/proc/sys/kernel/perf_event_paranoid'
The default value was changed to 2 in kernel 4.6
A value greater than 1 prevents gem5 from making
the syscall to perf_event_open"
Hi Abdelrahman,
> Is there a better way you can suggest using SPEC2017 in FS mode to
> evaluate my system on gem5?
>
No, there's not a better way, as far as I know :).
> My understanding is that the FS simulation is significantly slow. Any
> guidelines on how to make it as fast as possible?
Hi Meng,
It depends on the ISA you're using and the configuration of the system. For
instance, x86+classic caches is known to have some synchronization issues.
The transactional memory support only works with Arm, and I'm not sure
which memory system it requires.
What system are you trying to sim
Hello,
I don't believe there's a way to do that right now. However, in atomic
mode, many stats *are* skipped as they are only accessed in the "timing"
functions. I doubt it would make much performance difference. However,
that's just a guess, and I could be wrong.
Cheers,
Jason
On Wed, Mar 16, 2
Hi Liyan,
This looks like a stack address to me, so it won't appear in the objdump.
Since you're using SE mode, gem5 is controlling the physical address
mappings (not the OS). You can use the "Vma" debug flag to see all of the
virtual memory areas that gem5 creates/assigns. the "SyscallVerbose" f
Hello Abdelrahman,
Unfortunately, it's incredibly difficult to keep the development
environment for older versions of gem5 working. You may be able to find an
old dockerfile in those gem5 repositories that could help to recreate the
build environment. (I'm not sure if we were using docker at the t
Hi Tom,
I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags
which may help figure it out. It's possible that's the address of a
dynamically-loaded library as well.
Also, this trace looks like it came from Arm instead of x86. I don't
have as much experience looking at Arm addre
Hi Zicong,
1. I personally don't believe that CXL in SE mode would be very
interesting. From my point of view, CXL would be interesting only to
capture the OS and system-level effects. That said, you may be able to test
CXL.cache in SE mode.
2.
To implement the different protocols:
CXL.io: This
Hello Taiyu,
I would suggest reaching out to the VANS authors. Since this project is not
part of the gem5 repository, we have little control over the integration.
Cheers,
Jason
On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:
> Could you give me some advis
Hi Artyom,
You're absolutely right that the tutorial needs to be updated! The
website is also open source and managed via a git repo:
https://gem5.googlesource.com/public/gem5-website/. Updating this would be
a good way to get started contributing to gem5 :).
By the way, for the namespace, you ca
Hi Tom,
On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:
> Hi ,
> This may sound very generic, but i want to try some experiments with the
> out of order implementation. I came across few scenarios, which are listed
> below (any input would be helpf
Hi Ankit,
I would suggest modifying your python runscript instead of using command
line parameters.
https://www.gem5.org/documentation/learning_gem5/introduction/ may help
explain how to set parameters on SimObjects.
Cheers,
Jason
On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde wrote:
> Hi Gem5 Tea
Hi Vipin,
McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it
cannot be integrated in the same way. It's not really a timing simulator at
all. You can use gem5's statistics output as the "activity rate" which is
one of the inputs to McPAT. However, the other inputs (e.g., t
Hello,
I believe the problem is that gem5 tries to do too much automatically for
you! gem5 automatically creates a lot of the constructor/destructor codes.
Given all of this hidden/automatic code generation, it's difficult to know
exactly what's going wrong (for both you and for us).
That said, I
I just pushed a change that will make this error message better.
"fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the
error now says :).
See https://gem5-review.googlesource.com/c/public/gem5/+/59049
Cheers,
Jason
On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power
wrote:
>
Majid,
These are all great suggestions! Do you have a configuration file that you
would be willing to share? It would be a huge benefit to the community if
we had some better default configurations in the "examples" for gem5
configuration files.
We're also trying to use the new standard library f
Hi Markus,
I would expect gem5 to be at least 10,000-100,000x slower than your host.
So, if it takes 100 seconds on the host, then I would
expect between 1,000,000 and 10,000,000 seconds or more!
That's 277-2770 hours or 10-100 days!!
BTW, I actually think a 10-100,000x slowdown is on the low si
PM yaogang wrote:
> Hi Jason,
>
>
>
>Is there any roadmap (near future not long term) to take gem5 to multi
> thread accerleration?
>
>
>
> Regards
>
> Yao
>
>
>
> *发件人:* Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:
mpoint with gem5 v22? Thanks a lot!
>
>
>
> BR, Markus
>
>
>
> On 08.11.2022, at 20:10, Jonathan Kang wrote:
>
>
>
> Something as big as Spec typically wouldn’t be simulated as a whole but
> rather, using SimPoint on a cycle-accurate model.
>
>
>
>
I believe the problem is with the kernel binary you are passing in. It
needs to be the path to the binary (not a directory), and it must be the
uncompressed kernel binary, not the compressed binary.
Cheers,
Jason
On Tue, Nov 22, 2022 at 11:06 AM JASPINDER KAUR via gem5-users <
gem5-users@gem5.org
Hi Vipin,
The interface to gem5 isn't the command line, it's a python runscript. In
your python script, you can add parameters (e.g., with optparse) which are
accessible from the command line, but this shouldn't be considered the main
interface to modifying the parameters of gem5 objects. If you w
Hi Eliot,
Unfortunately, I don't have a direct answer for you. However, I want to say
that I appreciate you keeping the mailing list updated with your progress!
Cheers,
Jason
On Fri, Jan 6, 2023 at 10:07 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:
> On 1/4/2023 11:51 PM, Eliot Mo
Hi Zhengrong,
On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users <
gem5-users@gem5.org> wrote:
> Hi All,
>
> Our group has been using gem5 for architecture research for a long time,
> and we currently want to explore some ideas on modern multi-chiplet
> architectures, e.g. AMD's EPYC.
Hi Rajesh,
You can find all of the links in this json file:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/resources.json
It's not very user-friendly, but we're working on it :)
Cheers,
Jason
On Fri, Feb 17, 2023 at 10:15 AM Rajesh Shashi Kumar via gem5-users <
gem5-use
Hi Jonathan,
We just did a tutorial on how to use ELFies with gem5. See
https://looppoint.github.io/hpca2023/ for details.
We are able to load ELFies and run them in gem5. See
https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
for an example.
That said, we
Yes, that's correct.
Cheers,
Jason
On Thu, Mar 9, 2023 at 9:44 AM Jonathan Kang wrote:
> I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints.
> That’ll allow me to run it on an ARM Cycle Model.
>
>
>
> From the links you sent, it’s still Pin based and the resulting ELFies are
>
Hello,
This is a great question!
The short answer is I believe that the coherence protocol is correct.
(Though, there could always be unexpected bugs.)
The slightly longer answer: You are probably seeing that the store happens
before the load in "real" time. However, in the processors' view (i.e
Hi Xiang,
I would advise against using such old resources for current research. Using
an OS from a decade ago may not give you results that are accurate for
today's systems.
For "linux-bigswap2.img", this is just an empty disk image that was used as
swap space. You can probably use an empty file
Hi Jonathan,
Absolutely! You can set up a "bridge" which will take a subset of addresses
and route to a different gem5 port. If you can convert from the port
interface to the AXI, then it should "just work". Note that there are also
already bindings to SystemC/TLM in gem5 as well that could serve
Hi Jonathan,
You can put the bridge wherever you would like. For MMIO things, you can
put it after the point of coherence, which is where we usually put the "I/O
crossbar."
You can poke around in configs/examples and util/systemc for some examples.
Cheers,
Jason
On Wed, Apr 26, 2023 at 4:30 PM
Thanks
> Arun
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Yes, this is possible, and I believe it's already implemented for Arm.
>>
>> The best place to start is src/arch//tlb.cc
>>
>>
Hi Nick,
For teaching you may be able to get some inspiration from my class
assignments. Specifically, assignment 5 is about coherence:
https://jlpteaching.github.io/comparch/modules/gem5/assignment5/
All of the code for my assignments can be found here under different
branches for each assignmen
Hi Nick,
I think you have a typo. It's `gcr.io` as in "google *c*ontainer registry."
I believe you have an "e" instead of a "c" in your URL.
Cheers,
Jason
On Sat, Jun 10, 2023 at 7:52 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:
> Bobby,
>
>
>
> I tried your recommendation
Hi all,
You can use python multiprocessing with gem5. See
https://github.com/gem5/gem5/tree/develop/src/python/gem5/utils/multiprocessing
for details.
So, in theory, you can create scripts such that you can run `./gem5 run.py`
which will run a set of different experiments. You could potentially e
Hello,
I believe you would have to modify your compiler to emit the instruction to
avoid using embedded assembly.
Cheers,
Jason
On Tue, Jun 20, 2023 at 10:36 AM 中国石油大学张天 via gem5-users <
gem5-users@gem5.org> wrote:
> When I have customized a RISC-V instruction, I want to know how to make
> the
Hello,
You may also find the "Learning gem5" documentation
https://www.gem5.org/documentation/learning_gem5/introduction/ and the
bootcamp videos
https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3
useful.
Cheers,
Jason
On Tue, Jun 20, 2023 at 10:49 AM Eliot Moss via gem5-us
Full system mode is fully supported for RISC-V. There should not be any
problems with running pthreads on RISC-V.
(Side note: There could be a small bug in the RISC-V atomic instructions...
we're looking into it, but haven't been able to track it down.)
Cheers,
Jason
On Thu, Jun 29, 2023 at 4:05
Hi John,
The following may be helpful:
https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/
https://www.youtube.com/watch?v=OcXA1D4b1RA&t=3868s
Cheers,
Jason
On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:
> On 7/6/2
Hi Robin,
This may be helpful:
http://www.lowepower.com/jason/visualizing-spectre-with-gem5.html
For `warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented`, this is an AVX
(or SSE) instruction that gem5 doesn't implement.
Overall, I'm not sure if gem5 is vulnerable to meltdown. I think that the
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