Hello, Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board in the components library. See https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py
I am working on the CHI protocol. I have a WIP changeset that I could share. The final part I'm working on is getting DMA. That said, since MI_example and MESI_Two_Level work, there's evidence that any protocol should work. Cheers, Jason On Tue, Nov 2, 2021 at 3:29 AM Javier Garcia Hernandez via gem5-users < gem5-users@gem5.org> wrote: > Hello. > > Is Ruby supported on RISCV FS? > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
