Hi Deepak, Yeah, the cache disable bit may not work correctly in the page table walker/TLB. You can check the code there to see if that's what's going wrong.
You can also try adding an E820 entry to the workload object (e.g., https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/system.py#305) which marks that physical range as uncachable. I believe that works correctly. Cheers, Jason On Thu, Jun 17, 2021 at 4:02 AM Deepak Mohan via gem5-users < gem5-users@gem5.org> wrote: > Hi, > I'm doing some experiments using gem5 FS mode for x86. > In the FS mode I'm running a custom OS written for the requirements of > my experiment. I have added a PIO device to the x86 system which > responds to reads and writes to an address range. In the OS I have > mapped this device to a range in the PCI memory map region (@3GB). I > don't want this range to be cached, but when I add the cache hierarchy > to my FS simulation it seems that the device range is also cached. I > tried setting the C bit (Cache disable) in page table entries to > prevent this device range from getting cached, but it seems that > doesn't work. What can I do to prevent the address range of my device > from being cached , or am I doing something conceptually wrong ? Any > ideas / suggestions / pointers would be helpful. > > Thanks, > Deepak Mohan. > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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