Hi Fengze, No, there is no defined interface between different levels of the cache in Ruby. Ruby is a "black box" in some sense, with input on the CPU side and output on the memory side. See https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and https://www.youtube.com/watch?v=XTIrVBb86aM&ab_channel=JasonLowe-Power for more information.
Cheers, Jason On Mon, Oct 25, 2021 at 6:18 AM Fengze Yu via gem5-users < gem5-users@gem5.org> wrote: > > Hi > > What is the interface between L1 and L2 cache in Ruby cache coherence > model? Is there a clear defined interface, similar to the icachePort and > dcachePort between CPU and memory, between different levels of caches in > Ruby? > > > Thanks in advance > > Fengze Yu > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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