Hi Mike,
You should be able to change them through the command
line. If you want to change them in Python then yes, the
configs/common/Caches.py is what you're after, but fyi with the command
line below you're not selecting any caches.
Ali
On 06.05.2012 16:29,
Levine, Michael I wrote:
>
Hi,
You can use initparam to pass one parameter. Normally I would
have one rcS script per benchmark and use the initparam to select the
number (4) in this case.
Ali
On 07.05.2012 22:09, ef wrote:
> Is
it possible to pass any arguments to the rcS file?
> For instance on
the command line
EMM has an easily available kernel.
Ali
On 08.05.2012 10:01,
Samuel Hitz wrote:
> Hi Jason,
> Thank you for your answer. Is there
a reason why you recommended the VExpress_EMM rather than the
VExpress_ELT? I'm asking just out of curiosity, since both seem to be
fitting.
> Best,
> Samuel
Samuel,
The VExpress EMM memory map will likely be used by many
actual ARM devices in the future while the the ELT one will not be.
Ali
On 10.05.2012 04:04, Samuel Hitz wrote:
> Hi Jason,
> Since
I'm porting an operating system, I'm building my own kernel anyway. Is
there anything else
--take-checkpoints=,
or as another option
you can insert the opcode for the m5_checkpoint instruction (see
src/util/m5op_arm.S) into your kernel.
Ali
On 11.05.2012 03:28,
Samuel Hitz wrote:
> Hi there,
> Is there a possibility to create a
checkpoint during system startup, without having
t; ./build/ALPHA_FS/m5.opt configs/example/fs.py -n 4 -b canneal
>
> Thanks in advance
>
> On Mon, May 7, 2012 at 11:27 PM, Ali Saidi wrote:
> Hi,
>
>
> You can use initparam to pass one parameter. Normally I would have one rcS
> script per benchmark and use the init
I think you're going to have to debug a little bit and see if the cache is
responding and that isn't rescheduling the tick event, or if there isn't a
response and why.
Ali
On May 12, 2012, at 9:19 AM, Yuval H. Nacson wrote:
> Hello,
>
> I'm new to gem5.
> I'm trying to run 2 threads in ALPHA
> Obviously doesn't work. Any help would be greatly appreciated.
>
> On Sat, May 12, 2012 at 6:31 PM, Ali Saidi wrote:
> Take a look at the advanced bash scripting guide:
> http://tldp.org/LDP/abs/html/
>
>
> Pretty much:
> val=`m5 initparam`
> and -b Cannea
Hi Amine,
Could you try removing your build directory (rm -r
build) and re-running the first command (note: unless you're using
gem5-stable you'll want to run scons build/ALPHA/gem5.opt)?
Could you
make sure that you have all the following packages installed:
apt-get
install gcc g++ build-
You're going to have to get gdb hooked up to gem5 and see where that
address is coming from and why its bad. With alpha all the kernel
addresses should start with c, so some how something is going wrong.
You can also try sprinking printks or dprintks through the code to see
where the address
Yes, there isn't any back pressure here and there probably/maybeshould be. The
reason we've got away with it before is that normally the pressure comes from
the cpu itself. The number of outstanding translations is limited by the size
of the LSQ. That is why I find this to be strange. there is s
Hi Tony,
You should be able to handle all of what you need within the table walker. The
bit of code you're missing is that you need to save the drain event (de). In
addition, what needs to happen is that the TableWalker implementation of
drain() needs to cal the underlying DmaDevice implementat
Either is workable, but it might be easier to just do everything in virtual box.
Ali
On May 15, 2012, at 12:28 PM, wael Amr wrote:
> Hi Eng.Gabe,
>
> As i mentioned before i can't run gem5ing.py on mac os ,so i am really
> blocked.
>
> I am still confused what should i do to configure the who
Hi Amin,
See inline.
On May 16, 2012, at 12:31 AM, Amin Farmahini wrote:
> Hi All,
>
> I am trying to switch from an O3 core to a TimingSimple core using a pseudo
> instruction. I would like to do a cpu switching when the O3 core sees a
> specific pseudo instruction. Since that pseudo instruc
Hi Anderson,
I would suggest that you start with a disk image from gem5.org and modify it
rather than create one from scratch. If you want to create one from scratch
you'll need a disk image (ubuntu is fine, but all the startup scripts and
programs do take a while to run) and you'll need to cre
Steve, Nate,
Any ideas?
Thanks,
Ali
On May 3, 2012, at 1:46 PM, Sascha Bischoff wrote:
> HI,
>
> I have tried casting the Tick arguments as int, Tick and long from the
> Python. None of these work, and return “NotImplementedError” as before.
>
> The only success has been by creating a wrap
t; if it's a necessary assert:
>
> assert(device->getState() == SimObject::Running);
>
> Isn't the Draining state also a type of 'Running'? If it's draining, it
> should still be able to complete whatever actions it needs to to drain.
Yea, that is probably righ
Object::Running);
>
> Isn't the Draining state also a type of 'Running'? If it's draining, it
> should still be able to complete whatever actions it needs to to drain.
>
> Thanks,
> Tony
>
>
> On Sun, May 20, 2012 at 10:53 AM, Ali Saidi wrote:
&
Hi Nathanaël,
It's quite possible there is a bug. Unfortunately, I don't think anyone knows
the branch predictor code extremely well.
Please see inline.
On May 21, 2012, at 3:36 PM, Nathanaël Prémillieu wrote:
> Hi all,
>
> I'am currently looking at the branch prediction code.
>
> In the p
Generally it does, but it's up to the boot loader or in the case of
not using a boot loader the initCPU() code in the simulator to choose. I
think most real systems boot CPU0 as well, but that is just because it's
easier to start with 0 and increment than to start with n and hav eto
skip n later
I imagine you're seeing a combination of things. The main memory
image is compressed with gzip, so that reduces the file size
significantly. Also, I would check what input set you're using and if
you've actually selected the reference input set. The others do not use
800MB, and running the refer
Hi Tarun,
Looking at what you've run you've specified that stein should be read from
test.in stout should be directed to foo.out and that you should run bzip.out (I
assume this is the arm binary)? No options are being passed to the binary in
this case.
Assuming that testi.in provides some dir
You need to make sure you're running the same machine with qemu and
gem5. Make sure that you've set the --machine-type= to the appropriate
machine. Kernels aren't compatible between different variants as the
memory maps can be completely different. I don't know what platform
you've compiled your
On 24.05.2012 13:21, D K wrote:
> Hello,
> we are doing a project
on real-time scheduling on multi-core systems.
> Right now I am looking
for the possibility of using Gem5 as a simulation environment for
testing different scheduling policies for multi-core systems.
>
> For
the simulation we n
in, I'm not sure how to go about tackling that issue, either. I
>will continue to toy around with the machine-type and bare-metal
>options, and post any updates if I find a working solution. I would
>appreciate any help on the above mentioned issues.
>
>On Thu, May 24, 2012 at 3:54
It should work on gem5 with the ARM ISA.
Ali
On 25.05.2012
14:36, Diana Guttman wrote:
> Hello,
> Has anyone successfully run
SPECjbb in x86 fullsystem mode? Or do you know of any work which has run
SPECjbb using m5?
> I have been trying to run it but I am not sure if
it will be possible
re to see how these values are
> getting set in the first place.
>
> By the way, I am not sure how to hook up gdb to the kernel running on gem5?
> This is inside the kernel, so I was not sure how to run gdb on it.
>
> Thanks,
> Pritha
>
> - Original Message -
&g
simulate PMU(performance monitor unit)?
regards,
Dave
On Tue, May 29, 2012 at 10:37 AM, Ali Saidi
mailto:ali.sa...@arm.com>> wrote:
This looks like you're trying to run a semi-hosted binary (the svc with #22 as
the call number being heap info), not a syscall emulation binary. gem5 does
Hi Anirudh,
If you just specify --dual on the command line you'll
get two systems and you don't need to actually bother with modifying the
regression test you mention below, however you need to think about how
they'll connect together. We have PCIe based ethernet network interface
models, howe
get this done at some point, but I don't have an eta.
Ali
On 29.05.2012 11:25, Anirudh Sivaraman wrote:
> On Tue, May
29, 2012 at 11:05 AM, Ali Saidi wrote:
>
>> Hi
Anirudh, If you just specify --dual on the command line you'll get two
systems and you don't n
Hi Samuel,
I think you're right. Sorry about that.
Thanks,
Ali
On 29.05.2012 11:38, Samuel Hitz wrote:
> Hi there,
> I'm working
with gem5 for several months now, however I only lately updated to the
latest release and there was something added, which doesn't make sense
to me (and bre
Hi Nathanaël,
In SE mode VA == PA so no translation is required.
Thanks,
Ali
On 5/31/12 11:54 AM, "Nathanaël Prémillieu" wrote:
>Hi,
>
>I'm running gem5 in SE mode for the ARM architecture. I'm using the
>'arm_detailed' cpu type with --caches and --l2cache options activated.
>However, all the
eu wrote:
> Ok,
> Thanks for this answer.
> Is there a way to way to had a tlb in SE mode, to have a more accurate model ?
>
> Regards.
>
> Nathanaël
>
> Le 31/05/2012 18:00, Ali Saidi a écrit :
>> Hi Nathanaël,
>>
>> In SE mode VA == PA so no translation is
Anirudh,
You're not going to get anywhere using the VExpress_ELT platform. When I
committed it I thought it was going to become a standard, but it's been all but
abandoned at this point -- it should be removed from the repository. You can
add a ethernet and ide disk to the VExpress_EMM platform
the simulator maintains internally, and in FS mode
>> it uses the normal mechanism defined by the architecture.
>>
>> Gabe
>>
>> On 06/02/12 09:27, Ali Saidi wrote:
>>> There is no way to have one, "out-of-the-box." You'd need to do a fair
&
>
> Sorry about switching between top and bottom posts, gmail defaults to top.
>
> Originally I thought I was building the 38 kernel; however, because I
> did a "git checkout -b", I really only created a new branch
> identically to the HEAD - which is the 35 kernel. So, when I removed
> that bran
On Apr 24, 2012, at 3:46 AM, Fathallah-XID, Houssem wrote:
> Hi all, I am Gem5 beginner, I have run your bbench android example in FS
> mode, and I have been able to get the statistics without any problem.
>
> build/ARM/gem5.opt configs/example/fs.py -b bbench
> --kernel=vmlinux.smp.mouse.a
Hi Samuel,
It sounds like you're trying to use our bootloader with
the barrelfish OS. If you look at the code in
system/arm/simple_bootloader you can see what it's doing. This in
reasonably linux oriented (wait until you get an interrupt and read a
flag address). The address in question comes
On Jun 7, 2012, at 4:28 AM, Ira Ray Jenkins wrote:
> I've completed a few benchmark runs, and in looking at the stats I'm a
> little confused. Specifically regarding the translation buffers... The
> dtb is the "data", and the "itb" is the instruction, correct? Why then
> do the comments on many o
Do you want four copies of vpr?
In that case the command needs to
specify 4 instances like vpr-vpr-vpr-vpr
Ali
On 08.06.2012 14:40,
Bojun Ma wrote:
> Hi, All,
> I am trying to run SPEC2000 benchmark in
ARM_SE mode. I need to simulate a 4 cores system,So I used the command
line( take vpr
Not so much turned off as simply not present for the execution that generates
the checkpoint.
Ali
Sent from my ARM powered device
On Jun 10, 2012, at 8:54 AM, Ira Ray Jenkins wrote:
> Does this imply the caches can be turned off to checkpoint? And later
> turned back on? Or that you cannot ch
In many cases stats that are 0 aren't printed.
Ali
On Jun 11, 2012, at 7:41 AM, Ira Ray Jenkins wrote:
> At the beginning of my sim, I run m5 dumpresetstats, then every so
> often I call m5 dumpresetstatus again. The first call produces:
>
> system.realview.nvmem.bw_read 2
em.tol2bus-p0 ReadReq
> 0x4f000 RETRY
> ...
>
> I don't know if this happens because of my modifications (even if I don't how
> it can be related) or because I have stumble upon some bugs.
>
> Nathanaël
>
> Le 22/05/2012 04:56, Ali Saidi a écrit :
>
re the simulator start to loop).
>
> I have posted the
patch here: http://reviews.gem5.org/r/1268/Nathanaël
>
> Le 11/06/2012
15:21, Ali Saidi a écrit :
>
>> Hi Nathanaël, What SPEC2k6 benchmark
are you running when the simulator doesn't finish? Are you running in SE
Well, the good news is that it should'n be too hard to debug as it's
just looping and not making any progress. The bad news is I can only
make some guesses from the trace. It appears as though the L2 cache is
blocked (out of MSHRs). At least some of these responses are coming from
the L1 cache (
The O3 CPU counts the number of requests it's submitted and limits
it to the number set. I'm not sure how you got the trace you posted, but
in our model it's the CPU's responsibility to limit the number of
requests to the cache.
Ali
On 12.06.2012 15:40, Amin Farmahini
wrote:
> I only modif
I'm guessing that you're using an older version of gem5. That code
is a bit dated and the current version does a better job handling these
kinds of cases.
Ali
On 13.06.2012 10:23, Mahmood Naderan wrote:
>
Actually gem5/ext/libelf/SConscript
>
> Here is the output:
>
>
Checking for C head
Yes, they're informational and shouldn't be use for results. If you
want the number of instruction or ops executed you should look at the
stats attached to a cpu.
final_tick is supposed to be used for
matching up frame captures from a frame buffer to stats that go with it
and and the other are
d Naderan [mahmood...@gmail.com [7]] Sent: Wednesday,
June 13, 2012 5:31 PM To: sa...@umich.edu [8]; gem5 users mailing list
Subject: Re: [gem5-users] is it possible to use gcc/g++ 4.6.3 ?? 8821 I
use Is there any quik way to fix it? at ths time I am not ready to
update my repository due to modific
http://gem5.org/Download
Download the new system files and a
working config is in there. You should be able to build a working kernel
from that.
Ali
On 15.06.2012 16:05, David Gonzalez Marquez wrote:
> I must to modify some parts of the linux kernel in order to add a
pair features.
> I d
If there is a fixed number of packets you could put a m5 work begin operation
after each is successfully transmitted and terminate once the work begin count
exceeds a certain number. The functionality to terminate the simulation is a
parameter on the System object (work_begin_exit_count), but yo
Just like the error message says, it appears as though your linux
kernel is too old to run the binary that you've created. Libc normally
checks that the kernel is reasonably new and I imagine the kernel/libc
on the system you built the hello world program on is much newer than
the kernel you got
On 19.06.2012 13:06, Pritha Ghoshal wrote:
> Hi,
> I am getting a
kernel panic which I am not able to debug. The pc itself is getting
polluted.. I have added the trace of the panic at the end of the email.
> This is a snippet from the object dump of the kernel code.
>
>
fc5d51e8: 0
Either compile your code on an older system or compile a newer
kernel for use with gem5.
Ali
On 19.06.2012 14:09, Victor Zhang
wrote:
> What are some possible solutions? Is there a newer kernel
available to download
> or can I compile via older versions?
>
>
_
It looks like you'r running into an issue with a newer compiler and
an older version of gem5. You should give the development version a try.
Ali
On 20.06.2012 15:25, Matthew Catanzaro (RIT Student) wrote:
>
Getting this build error when trying to build ALPHA_FS. Is scons
>
attempting to bu
Hi Rafael,
The ELT platform was removed because there isn't a linux kernel available for
it. IF you need it you can add the code back from a previous change set in the
repository. It would be best to switch to the EMM model.
Thanks,
Ali
On Jun 20, 2012, at 1:58 PM, Rafael Garibotti wrote:
> H
mill/test_gen3.445.gobmk.score2.14.2009/gobmk_base.armv7_nothumb-gcc
--input=score2.tst -o "--quiet --mode gtp" --output=score2.out
--errout=score2.err The only modification I have made to the se.py
script is to have a physical memory of 2048MB instead of 512MB. I have
put the DPRINT statement
It completely depends on what consistency model you're going for.
The current code doesn't support sequential consistency, but the
load-load ordering that is enforced is inline with ARMs ordering
requirements.
Ali
On 21.06.2012 17:09, Dibakar Gope wrote:
> Hi
All,
>
> I was skimming throu
HI Dibakar,
I'd have to think carefully about it, but you may be
right about TSO. I'd hope that someone who is more familiar with x86
could respond.
Thanks,
Ali
On 22.06.2012 07:46, Dibakar Gope
wrote:
> Hi Ali,
>
> Thanks for the response. Ok, I got the point. I
thought that since th
Hi Andrea,
Yes that sounds like a bug. All threads need to share a zero reg, or the zero
reg needs to be checked for each thread. I'm curious how that worked with
alpha.
Thanks,
Ali
Sent from my ARM powered mobile device
On Jun 22, 2012, at 6:22 PM, Andrea Pellegrini
wrote:
> Hi all,
>
This looks like you're trying to run a semi-hosted binary (the svc with #22 as
the call number being heap info), not a syscall emulation binary. gem5 doesn't
currently support executing semi-hosted code, but if you compile a static linux
executable you can run that. As another option, if you hav
I doubt /m5/bin/m5 exists, however /sbin/m5 probably does.
Ali
On Jun 25, 2012, at 9:12 AM, Anusha wrote:
> When I try to create checkpoint for canneal I get the following message
>
> Just saw element: 10
> netlist created. 10 elements.
> sh: /m5/bin/m5: No such file or directory
> [HOOK
gt; squashed would mean that all subsequent loads are squashed as well.
>
> --
> Nilay
>
> On Fri, June 22, 2012 8:47 am, Ali Saidi wrote:
>>
>>
>> HI Dibakar,
>>
>> I'd have to think carefully about it, but you may be
>> right about TSO.
Hi,
If you're using m5-stable you need to build bulid/ARM_SE/statetrace
Ali
On Jun 21, 2012, at 5:04 AM, fengye wrote:
> Hi,everyone!
> I used the gem5-stable to study the statetrace tool. there is a problem for
> me in the following experiment. How can I solve the problem,Thanks.
>
> root@f
It looks like you haven't managed to find a lib python and libz to link with.
Ali
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] On Behalf Of
Ranga, L Udaya [udayara...@ti.com]
Sent: Monday, June 25, 2012 1:59 AM
To: gem5-users@gem5.org
S
Hi Dave,
You need to remove the ide and ethernet devices from the
VExpress_EMM config in src/dev/arm/RealView.py. Hopefully there will be
instructions on how to compile a kernel with PCIe support soon that will
make use of these devices.
Thanks,
Ali
On 27.06.2012 10:21, David
Roberts wro
Hi Nathanael,
The issue with the change below is that the address
could be correct, however the flag bits (e.g. thumb state) or the
correct IT state could be wrong. Would it be possible for you to dig a
little deeper and see what part of the the PCState objects are causing
the mispredicts to h
into no-ops or prefetches,
so I'm not too surprised that this generally worked (though I also would
not be surprised if there were some corner cases that don't work that we
never identified). Ideally all ISAs would decode instructions with
zero-reg targets like this, so that the zero reg wou
Hi Nathanaël,
So are you saying that everything is predicted
correctly, however the check is truly wrong in this case?
Thanks,
Ali
On 27.06.2012 12:03, Nathanaël Prémillieu wrote:
>
>From what I have understand on the example I have worked on to detect
>
the bug, the predicted address i
he front of the commit, is there any other fundamental difference
of using ReExec in comparison to the squashDueToMemOrder() other than
this?
>
> Thanks,
> --Dibakar
>
> On 06/25/12, Ali Saidi wrote:
>
>>
ARM just requires load-load ordering (which is stronger than alpha). x
Hi Everyone,
We've just updated the stable repository with a bunch
of new changes and bug fixes. Mercurial users can just just hg
pull/update to get the latest code. See http://gem5.org/Download for
more information.
The SE and FS merge that is described below changes
how gem5 is compiled. T
Hrm... Anyone have an idea how to fix this?
Ali
On 27.06.2012
14:27, Nathanaël Prémillieu wrote:
> Yes, the PC (the _pc in the
PCState structure) are the same, but the
> check checks also if the NPC
(the _npc int the PCState structure) are
> the same. And here this is
not the case, hence
On 29.06.2012 13:30, Anirudh Sivaraman wrote:
> and gem5 says this
:
> panic: Write request to unknown register number: 0x5808
> @ cycle
489718882000
> [write:build/ARM/dev/i8254xGBe.cc, line 679]
You seem to
have stumbled across some unimplemented functionality. It can be as
simple as ignori
ARM and linux need to be passed as strings and they need to be lower
case.
Ali
On 29.06.2012 15:16, Nyunyi Tshibangu wrote:
> Hello,
>
I am trying to run spec2000 in SE mode using ARM simulator but I am
getting error just trying to compile the benchmark.
> here is the
errror message:
>
Hi Nathanaël,
How have you configured your cache?
Thanks,
Ali
On Jul 1, 2012, at 1:47 PM, Nathanaël Prémillieu wrote:
> Hi,
>
> I have a problem that has appeared with the changeset 9084:ace8383f2b7e.
> gem5.fast segfaults and with gem5.debug, an assert statement breaks.
> I have tested with t
Hi Pritha,
The m5 binary should say the period is in ns, not
ticks.
Thanks,
Ali
On 01.07.2012 13:10, Pritha Ghoshal wrote:
>
Hi,
>
> I am using dumpresetstats in my .rcS script, but I have a
doubt in that. The definitions are as follows:
>
> * resetstats
[_delay_ [_period_]]: Reset
I still haven't seen in happen. How long does it take for it to
occur? Can you make it happen during boot?
Thanks,
Ali
On
02.07.2012 05:17, Nathanaël Prémillieu wrote:
> Hi,
>
> It's the
default configuration (--caches --l2cache) with the
> arm_detailed cpu
model.
>
> Nathanaël
Hi Nikos,
I'd be worried that you could have a case where the NPC
was never checked and the cpu would mispredict a branch but never
understand that it had. If you do it does it work? I'd expect that you
might not actually branch at the second beq.
Thanks,
Ali
On
02.07.2012 15:56, Nikos N
Likely the entire instruction footprint fits in the L1 i cache and
there is very little re-use on the data side. Removing the L2 probably
lowers the access time to main memory by a substantial amount which
improve performance.
Ali
On 02.07.2012 20:06, Nyunyi Tshibangu
wrote:
> I am having
This distinction between SE and FS is gone you need to remove the _FS part from
your command line.
Ali
On Jul 8, 2012, at 11:20 AM, Munawira Kotyad wrote:
> Hi,
>
> I am trying to compile gem5 in X86_FS mode and am getting the following error:
>
> ece% scons build/X86_FS/gem5.opt
> scons: Rea
Hi Samuel,
You can use the gem5 op rpns() to get a count in ns since the start of
simulation. Depending on the resolution you need there are a variety of
counters and timers that you can read. Long term, we'll try to implement the
performance extensions, but it's got a lot of tentacles into thi
It might be… Korey, any thoughts?
I'm not that familiar with the in order cpu, but it either needs to store the
predicted address or one previous to it in all cases. My only worry with this
change is that with the RAS is used you'll end up unnecessarily incrementing
the PC and mispredicting the
On 11.07.2012 17:15, Anthony Gutierrez wrote:
> Hello,
> I am
having a problem when switching between two arm_detailed model CPUs. I
am getting the following assertion failure:
>
> m5.opt:
build/ARM/dev/dma_device.cc:90: virtual bool
DmaPort::recvTimingResp(Packet*): Assertion `pendingCount
On 11.07.2012 03:35, Samuel Hitz wrote:
> Hi there,
> I have a
problem reading/writing to the SYSFLAG register when caches are turned
on. I wan to write the entry point for the new core in there, which
works fine when caches are turned of. However when caches are turned on
I get
>
> gem5.de
On 12.07.2012 02:45, Anthony Gutierrez wrote:
> I've determined
this is because drainEvent()->process() is being called when the port
has properly drained. However, once it signals that it has drained, it
gets another request.
So the issue here isn't the tlb, but it's another
component in the
and the real value if I disable caches. I traced cache
accesses and I didn't give me any clues. You said once that Gem5 handles
cache coherency on it's own. Do you have any ideas how this can happen
and what I could do to fix it?
> Best,
> Samuel
>
> On Thu, Jul 12,
2012 at 12
then instead?
>
> On Thu, Jul 12, 2012 at 3:15 PM, Ali
Saidi wrote:
>
>> Did one of them save/read it
with caches disabled?
>>
>> Ali
>>
>> On 12.07.2012 08:07, Samuel
Hitz wrote:
>>
>>> Ok I digged a little deeper now. The problem isn't
t
new ReExec;
> } else {
> // If
a older load checks this and it's true
> // then we might have missed
the snoop
> // in which case we need to invalidate to be sure
>
ld_inst->hitExternalSnoop = true;
>
> if (needsSC == true){
>
>
ld_inst->fault = new ReExec
Hi Tony,
It's a bug. generateDisassembly() needs to be overwritten for the mrc/mcr ops
with code that produces the correct assembly.
Thanks,
Ali
From: Anthony Gutierrez mailto:atgut...@umich.edu>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Wednesday, July 18, 2012 8:
The function tracing code in the cpu might help (see the
function_trace and function_trace_start option on the cpu model).
However, they' only support kernel level symbols at the moment. You
could use the loadsym m5 op to load some other symbols into gem5 or you
could try something else to get u
Hi Amin,
You can see my previous email about function tracing. For
SE mode code it probbaly will solve your issues.
Thanks,
Ali
On
21.07.2012 02:34, Amin Farmahini wrote:
> Hi,
>
> I would like to
profile program code (compiled for ARM ISA) to get function call timings
and total cycle
All models should boot in <1h, although there is no particularly good reason to
boot the OS with the O3 cpu. Normally people boot linux with a atomic simple
CPU, take a checkpoint and then switch to the O3 cpu to run their application
of interest.
We have regression tests that run weekly using
Could you try and run with opt instead of fast? You should only run
fast if you've successfully run a simulation before or run something
very similar to it. Having asserts and additional debugging is helpful
in these situations. Clearly something has gone wrong because Linux
thinks the device is
Could you give it a run through valgrind and see if it shows
anything?
Thanks,
Ali
On 24.07.2012 13:55, Andrea Pellegrini
wrote:
> Hi all,
> I am facing a bizarre issue w/ X86, SE, O3.
> On
my laptop the simulator works fine, but when I run gem5 on our
simulation pool I almost always g
On 25.07.2012 10:18, Anusha wrote:
> Has anyone been successful in
creating checkpoint in timing mode and restoring in detailed mode with
current version of gem5? (9123- 281b3ac0e0a1)
>
> Thanks,
>
Anusha
You should create checkpoints in atomic mode without caches.
Ali
___
On 25.07.2012 10:03, Nilay Vaish wrote:
> On Tue, 24 Jul 2012,
Romulo Curty Cerqueira wrote:
>
>> In practice I really received error
messages when I tried to simulated more than 4 CPUs in ARM FS mode, as
follows:
>
>> ... ARM ==> gem5.opt: build/ARM/dev/arm/a9scu.cc:66:
virtual Tick A9SCU::
On 26.07.2012 19:44, Amin Farmahini wrote:
> Hi,
>
> I'd like to
change the latency of a couple of Neon instructions. I started with VLD1
instruction which is called ldrNeon in Gem5. This instruction is
classified as a "FloatAdd" opClass. So I can modify the latency (opLat)
of "FloatAdd" clas
On 01.08.2012 10:45, Kiyeon Lee wrote:
> Hi.
>
> I am trying to
run a full-system multicore simulation using the ARM "VExpress_EMM"
platform modeled in gem5. I am using the latest source codes from the
gem5 repository.
>
> I configured the system to have 4 processor cores
and use the class
There is some issue with the o3 cpu not re-executing this load
before commit (because it's uncacheable). You'll need to track the
sequence number (sn) through execution in the O3 cpu and see why it
wasn't re-executed and debug it.
Thanks,
Ali
On 06.08.2012 07:55,
Ali chaker wrote:
> Hi,
You could try using taskset (I'm not sure if it's on the disk
image), but it does the same thing as m5 pin.
taskset 0x1 $bench0 &
taskset 0x2 $bench1 &
taskset 0x4 $bench2 &
Ali
On 07.08.2012
19:27, Cookie wrote:
> To whom it may concern,
> I tried to run 2
spec benchmarks on a 2-co
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