On 11.07.2012 17:15, Anthony Gutierrez wrote:
> Hello, > I am having a problem when switching between two arm_detailed model CPUs. I am getting the following assertion failure: > > m5.opt: build/ARM/dev/dma_device.cc:90: virtual bool DmaPort::recvTimingResp(Packet*): Assertion `pendingCount >= 0' failed. > Program aborted at cycle 5403285000 > As can be seen from the following trace, the switch_cpu is attempting to send a read request for 0xfffa7c4, shortly after it says it's "Done". A switchout occurs and the cpu attempts to send a read request for addr 0x7ffc, shortly after it says "Failed". It does a retry then says "Done". Later it attempts a read response for both of these addresses, however the pendingCount is only 1, thus leading to the assertion failure. > I tried forcing the drain functionality to only drain when transmitList.size() == 0, both inside drain() and when processing the drainEvent, this had no effect. I'm not too familiar with how the DMA code should work so any ideas would be appreciated. One thing that I noticed is that inside of the do-while loops inside both sendDma() and recvRetry() when the transmitList is popped, the pendingCount isn't decremented for Timing mode. Should it be? Also, another thing that is strange is the the drainEvent is only processed if state == Enums::atomic. > 5403270500: system.switch_cpus.itb.walker.dma: Starting DMA for addr: 0xfffa7c4 size: 4 sched: 0 pendingCount should be incremented here and sholud be > 1... > 5403270500: system.switch_cpus.itb.walker.dma: --Queuing DMA for addr: 0xfffa7c4 size: 4 > 5403270500: system.switch_cpus.itb.walker.dma: Attempting to send ReadReq addr 0xfffa7c4 > 5403270500: system.switch_cpus.itb.walker.dma: -- Done > 5403270500: system.cpu.itb.walker.dma: Starting DMA for addr: 0x7ffc size: 4 sched: 0 > 5403270500: system.cpu.itb.walker.dma: --Queuing DMA for addr: 0x7ffc size: 4 > 5403270500: system.cpu.itb.walker.dma: Attempting to send ReadReq addr 0x7ffc > 5403270500: system.cpu.itb.walker.dma: -- Failed: queued > 5403272000: system.cpu.itb.walker.dma: Retry on ReadReq addr 0x7ffc > 5403272000: system.cpu.itb.walker.dma: -- Done > 5403272000: system.cpu.itb.walker.dma: TransmitList: 0, backoffTime: 0 inRetry: 0 es: 0 > 5403282500: system.cpu.itb.walker.dma: Received response ReadResp addr 0xfffa7c4 size 0x4 pending cnt 1 It doesn't get decremented until here, so the switch should have never been allowed to happen. 5403285000: system.c > div>Tony > > It would be good to add some debugging around the src/pythom/m5/simulatie.py:drain(root) to see when drain is ca . It should have been called and the code should have never let the drain happen. Are you sure you're draining all objects in the system? Ali
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