Hi everyone,
If you want to inspect the configuration there is also a PDF produced by dot
(graphviz) if you have the pydot package installed on your system. This happens
automatically when running the simulator if the package is available. You could
envision starting from this dot description a
Hi Tony,
Could you give this one a go: http://reviews.gem5.org/r/1535/
It seems to solve the problem on my end.
Andreas
From: Anthony Gutierrez mailto:atgut...@umich.edu>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Monday, 5 November 2012 21:08
To: "gem5-users@gem5.or
Yes. And I hope to add a draining regression soon.
On Nov 7, 2012 3:29 AM, "Andreas Hansson" wrote:
> Hi Tony,
>
> Could you give this one a go: http://reviews.gem5.org/r/1535/
>
> It seems to solve the problem on my end.
>
> Andreas
>
> From: Anthony Gutierrez mailto:atgut...@umich.edu>>
> Reply
Much awaited!
I've bumped the patch as I forgot to check if there was already writeEvent
scheduled. Please give it another go and if you're happy then a "Ship it" would
be great :)
Andreas
From: Anthony Gutierrez mailto:atgut...@umich.edu>>
Reply-To: gem5 users mailing list
mailto:gem5-users@
Hi guys,
I was playing with gem5 (full system simulation) and found one
interesting feature.
If you make some changes to the disk image (using mount command on the
host) and restore your simulation using previously saved checkpoint
you may not find your changes in the simulated filesystem.
The mai
Can you provide some more information? What is your command line? Does the
simulation stop or fault? Does BBench ever start, what does the frame
buffer show?
That may be a warning that can be ignored.
-Tony
On Wed, Nov 7, 2012 at 2:42 AM, Aparna Mandke wrote:
> Hi,
> I am using ICS image and An
On Tue, 6 Nov 2012, Marko Zivkovic wrote:
The difference should be the communication latency between cores vs
CPUs, synchronization in cache memory between cores vs CPUs... Currently I
can pass --num-cpu but I would like heterogeneous setup( cores of CPUs with
different frequencies). Currently I
Hi,
I am running gem5 with ruby on FS mode. I found very large number of
simulated cycles (or sim_seconds). For example, I ran SPEC2006 benchmarks:
sphinx3 and xalancbmk simultaneously on a 2-core CMP for 500,000,000
instructions (--maxinsts=5) from a checkpoint (17,000,000,000,000).
As s
As Steve mentioned, the usefulness of the GUI is probably limited to "novice"
users (people with limited gem5 experience). That is my target audience.
Andreas -- your suggestion is great, as I am separately working on a similar
project: manipulation of graphs (node and edge placement, connectivi
Hi,
I just want to mention if it is possible because of timingCPU I used?
Somehow I cannot restore checkpoints using O3CPU. Is it the possible reason
or not? Can anyone tell me how to restore checkpoints with O3CPU with ruby?
Thanks,
Yingying
On Wed, Nov 7, 2012 at 12:33 PM, Cookie wrote:
> H
Hello,
I'm interested in running the RAMSpeed benchmark
http://alasir.com/software/ramspeed/
http://www.alasir.com/software/ramspeed/ramspeed-2.6.0.tar.gz
for x86, ideally for both syscall emulation mode and full system mode.
# I installed gem5
cd ~
hg clone http://repo.gem5.org/gem5
cd ~/gem5
sc
I forgot to mention that I did read
http://gem5.org/Compiling_a_Linux_Kernel
and
http://gem5.org/Linux_kernel
but they don't seem to answer what I think I should be asking.
Ben
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Payne, B
Hi Benjamin,
It would be great if you have some brain power (and time) to spend on
this. Visual feedback is always a great help, even if it is not used to
configure the system, but rather just observe it. The config.dot.pdf is
exactly what I'm referring to. We could change from PDF to something mo
Hello
I was wondering if you could help me figure out how can I build a c project
that has multiple parts with math.h and other libraries. I used gem5.fast for
building gem5. And then build "hello" and was able to see the result.
I would most appreciate your help.
Thank you,
Best regards,
Pa
Hello Fernando,
Thanks for your guidance.
Regards,
Shervin
---
Hello,
It would be interesting comparing the performance stats produced by gem5
for each core. If they are approximately the same, McPAT is taking into
account the physical distributio
Hi all,
I have some questions about MSHR. In my configs/common/Caches.py, L1Cache
class, I set mshrs=10, tgts_per_mshr=20. Does that mean for each core I
have 10 mshrs or for the whole system I have 10 mshrs? Another question is
there any function can check whether each MSHR is full or not?
Than
Hi All
I need to run Gem5-FS mode on multiprocessor ARM.
what about the configuration steps to build the architecture and also building
multiprocessor linux for ARM.
BR
Abbas
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Hi all,
I think I found in mshr_queue.hh, there is a function called isFull() which
can tell whether MSHR is full or not. My following question is that: I run
with ruby+alpha+garnet. Will this MSHR still work with Ruby or it just work
with simple classic memory? Also is there any way to diffe
Hello,
When I enable stride prefetcher on L1 dcache, and run timing mode on 4
cores configuration,
The stats.txt shows that only one core (core1) has prefetch statistics.The
number are zero on other core's prefetcher.
system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_identified
10455
Hello,
I want to simulate two SPEC 2006 benchmarks in SMT processor. (SE mode) I
noticed that only detailed and inorder cpu type support SMT. Since SPEC 2006 is
too large to run to completion, I have to fast forward to some region of
interest. But fast forward runs in atomic mode. I was wonde
After the fast-forward, gem5 will switch the cpu to detailed or inorder
mode, which can satisfy your requirement.
-Tao
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Fangfei Liu
Sent: Wednesday, November 07, 2012 11:32 PM
To: gem5-users@gem5.org
Subjec
Thanks for your reply. Since before the switch, it runs in atomic mode with
SMT. Does it matter?
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
Tao Zhang [tao.zhang.0...@gmail.com]
Sent: Wednesday, November 07, 2012 11:45 PM
To: 'gem
I didn't get your concern. What do you worry about? The atomicCPU can
quickly fast-forward the benchmark to your ROI while it will cost much more
time if detailed or inorder cpu are used to complete the fast-forward.
-Tao
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org
Hi,
In my understanding, fast-forward is done by running the program in atomic cpu
mode. That means for the first X instructions, gem5 simulates SMT processor in
atomic mode, but it's supposed not to be able to simulate SMT in atomic mode.
Have you ever tried to do fast-forward for SMT proces
I never use SMT mode after the fast-forward. But I think there is no
difference between O3CPU with/without SMT ( I did use ordinary O3CPU after
the fast-forward). You can refer to configs/common/Simulation.py to see how
fast-forward works. Basically, the system maintains two cpu lists, one
atomic a
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