On Fri, 8 Jun 2012, Ali chaker wrote:
if I've understood, the cache miss latency is calculated during the
simulation.I've found the following formula for misslatemcy in
cache_impl.hh file:
*completion_time = tags->getHitLatency() +(transfer_offset ?
pkt->finishTime : pkt->firstWordTime);*
*miss
if I've understood, the cache miss latency is calculated during the
simulation.I've found the following formula for misslatemcy in
cache_impl.hh file:
*completion_time = tags->getHitLatency() +(transfer_offset ?
pkt->finishTime : pkt->firstWordTime);*
*missLatency[target->pkt->cmdToIndex()][target
On Thu, 7 Jun 2012, Ali chaker wrote:
cache hitlatency is the time between sendind address and data returning
from cache and cache misslatency is the time between sending address and
data returning from next-level cache/memory.
Really!
Think of a three level hierarchy (L1 cache, L2 cache a
cache hitlatency is the time between sendind address and data returning
from cache and cache misslatency is the time between sending address and
data returning from next-level cache/memory.
BR,
Ali Chaker
2012/6/7 Nilay Vaish
> On Thu, 7 Jun 2012, Ali chaker wrote:
>
> Thanks!
>>
>> I need th
On Thu, 7 Jun 2012, Ali chaker wrote:
Thanks!
I need this because I have this cache latency (cycle) configuration:
CPU -- L1---L2--DRAM
10 20 (Hit the L2)
10 29100 (Miss the L2)
BR,
ALI CHAKER
2012/6/7 Nilay Vaish
On Th
Thanks!
I need this because I have this cache latency (cycle) configuration:
CPU -- L1---L2--DRAM
10 20 (Hit the L2)
10 29100 (Miss the L2)
BR,
ALI CHAKER
2012/6/7 Nilay Vaish
> On Thu, 7 Jun 2012, Ali chaker wrote:
>
>
On Thu, 7 Jun 2012, Ali chaker wrote:
Hello,
I found that there is only one cache parameter for the latency. Is it
possible to configure the memory cache with two different latency values
??(misslatency and hitlatency)?
I don't think that is possible as of now. But why do you want to hav
